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Reducing SRAM Power Using Fine-Grained Wordline Pulse Width Control

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Nanometer Variation-Tolerant SRAM

Abstract

In the previous chapters, we explored how process variations affect memory operation and how circuit techniques help provide variation tolerance. In this chapter, we look at variation-tolerant architectures and propose fine-grained wordline pulse width control to reduce the memory power. Section 4.1 gives an overview of variation-tolerant memory architectures and system approaches. Section 4.2 describes the problem of memory power consumption. In Sect. 4.3, we derive statistical models for memory yield and array power consumption and show the tradeoff between yield and power metrics. In Sect. 4.5, we describe the proposed solution which combines memory built-in self test (BIST) with programmable delay elements in a closed loop to reduce the power consumption. In Sect. 4.6, we present the statistical simulation flow used to estimate power savings using the proposed system (applied for memories in industrial 45 nm technology), and design considerations related to the proposed system. In Sect. 4.7, we summarize our findings.

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Notes

  1. 1.

    The statistical models are provided by the foundry, and the statistical data are extracted from measuring a large sample of bitcells as shown in [27]. Random WID variations are reflected in the Spice model by varying \(V_\mathrm{th}\), \(W\), \(L\) and other parameters of the bitcell devices according to the measured statistics.

  2. 2.

    Here, we assume that all memories are accessed simultaneously. For our analysis, this is a fair assumption since we do not make any assumptions related to how the system accesses these memories. Nevertheless, the same simulation flow can be used if the switching activity for each memory is known.

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Authors and Affiliations

  1. Qualcomm Incorporated, 5775 Morehouse Drive, SanDiego, CA, 92131, USA

    Mohamed H. Abu-Rahma

  2. Electronics Engineering Department, School of Sciences and Engineering, The American University in Cairo, AUC Avenue, New Cairo, 11835, Egypt

    Mohab Anis

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  1. Mohamed H. Abu-Rahma
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Correspondence to Mohamed H. Abu-Rahma .

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Abu-Rahma, M.H., Anis, M. (2013). Reducing SRAM Power Using Fine-Grained Wordline Pulse Width Control. In: Nanometer Variation-Tolerant SRAM. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-1749-1_4

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  • DOI: https://doi.org/10.1007/978-1-4614-1749-1_4

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