Co-Optimization of Latches and Clock Networks

Abstract

Optimizations developed in earlier chapters affect many aspects of physical synthesis, but often target sequential elements, which particularly impact circuit performance. In order to obtain synergies between these optimizations, we explore the infrastructure for physical synthesis used by IBM for large commercial microprocessor designs. We focus our attention on a very challenging high-performance design style called large-block synthesis (LBS). In such designs latch placement is critical to the performance of the clock network, which in turn affects chip timing and power. Our research uncovers deficiencies in the state-of-the-art physical synthesis flow vis-à-vis latch placement that result in timing disruptions and hamper design closure. We introduce a next-generation EDA methodology that improves timing closure through careful latch placement and clock-network routing to (i) avoid timing degradation where possible, and (ii) immediately recover from unavoidable timing disruptions. When evaluated on large CPU designs recently developed at IBM, our methodology leads to double-digit improvements in key circuit parameters, compared to IBMs prior state-of-the-art methodologies.