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Single-Ended SRAM Bitcell Design

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Robust SRAM Designs and Analysis

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Abstract

In this chapter, a case study of six-transistor (6T) Single-Ended Static Random Access Memory (SE-SRAM) bitcell with an isolated read-current path and its word-oriented array organization, suitable for low-V DD and low-power embedded systems is presented. The SE-SRAM has a strong 2. 65 × worst-case read Static Noise Margin (SNM) compared to a standard 6T bitcell and equivalent to an 8T bitcell from existing literature. The previously proposed single-ended bitcell topologies and their advantages and disadvantages are also highlighted with respect SE 6T SRAM bitcell. The SE 6T bitcell and its word-orientation, and how it departs from the existing topologies are discussed in detail. A comparison of noise margins, power and performance with standard 6T and 8T SRAM bitcells is also presented.

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Authors and Affiliations

  1. Indian Institute of Information Technology Design and Manufacturing, Dumna Airport Road, Jabalpur, India

    Jawar Singh

  2. University of North Texas, Discovery Park, 3940 N. Elm, Room F247, Denton, USA

    Saraju P. Mohanty

  3. University of Bristol, Merchant Venturers Building Woodland Rd., Bristol, UK

    Dhiraj K. Pradhan

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  1. Jawar Singh
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  2. Saraju P. Mohanty
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  3. Dhiraj K. Pradhan
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Singh, J., Mohanty, S.P., Pradhan, D.K. (2013). Single-Ended SRAM Bitcell Design. In: Robust SRAM Designs and Analysis. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-0818-5_3

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  • DOI: https://doi.org/10.1007/978-1-4614-0818-5_3

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