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Design Metrics of SRAM Bitcell

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Robust SRAM Designs and Analysis

Abstract

This chapter presents the basics of standard 6T SRAM bitcell and simulation setups for measurement of bitcell read and write stability metrics. Different static and dynamic stability metrics are investigated. Static stability metrics includes conventional butterfly curves obtained from the voltage transfer characteristics, the N-curve based metrics and their simulation setup for read and write stability are also discussed. The static stability metrics for large scale dense cache SRAM measured from bitline, wordline and bitcell supply voltage are also presented in this chapter. Apart from static stability metrics commonly used in SRAM design and development, dynamic stability metrics are also presented along with their simulations setups. Detailed simulation results and illustrations for static and dynamic stability metrics are the main focus of this chapter.

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Authors and Affiliations

  1. Indian Institute of Information Technology Design and Manufacturing, Dumna Airport Road, Jabalpur, India

    Jawar Singh

  2. University of North Texas, Discovery Park, 3940 N. Elm, Room F247, Denton, USA

    Saraju P. Mohanty

  3. University of Bristol, Merchant Venturers Building Woodland Rd., Bristol, UK

    Dhiraj K. Pradhan

Authors
  1. Jawar Singh
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  2. Saraju P. Mohanty
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  3. Dhiraj K. Pradhan
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Singh, J., Mohanty, S.P., Pradhan, D.K. (2013). Design Metrics of SRAM Bitcell. In: Robust SRAM Designs and Analysis. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-0818-5_2

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  • DOI: https://doi.org/10.1007/978-1-4614-0818-5_2

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  • Publisher Name: Springer, New York, NY

  • Print ISBN: 978-1-4614-0817-8

  • Online ISBN: 978-1-4614-0818-5

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