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Low-Power DRAM

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Green Computing with Emerging Memory

Abstract

Dynamic random access memory (DRAM) is a volatile random access memory and the memory cell consists of a cell transistor and a capacitor [1–3], as shown in Fig. 5.1. The cell transistor is used to connect a storage node (N) and a data-line (DL) by activating a word-line (WL), while the capacitor, connected between N and the plate (PL), stores information. The signal charge stored in the capacitor is reduced by the leakage currents of the memory cell, and this reduction causes data loss. To avoid this, a refresh operation that will be explained later is periodically required and the refresh interval is determined by storage node capacitance (C S). The signal voltage developing on the floating DL after WL is activated is also determined by C S. Therefore, higher capacitance (>20 fF) is crucial to achieving low standby power and stable sensing operation [4].

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Authors and Affiliations

  1. Central Research Laboratory, Hitachi Ltd, Tokyo, Japan

    Akira Kotabe

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  1. Akira Kotabe
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Correspondence to Akira Kotabe .

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  1. Hitachi Ltd, Chief Researhcer, Life Science Research, Tokyo, Japan

    Takayuki Kawahara

  2. , Hitachi Ltd, Central Research Laboratory, 1-280 Higashi-Koigakubo Kokubunji, Tokyo, 185-8601, Japan

    Hiroyuki Mizuno

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Kotabe, A. (2013). Low-Power DRAM. In: Kawahara, T., Mizuno, H. (eds) Green Computing with Emerging Memory. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-0812-3_5

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  • DOI: https://doi.org/10.1007/978-1-4614-0812-3_5

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