Abstract
As discussed in Part II, process-induced variability has huge impacts on chip leakage currents, owing to the exponential relationship between subthreshold leakage current I sub and threshold voltage V th as shown below[172],
where I s0 is a constant related to the device characteristics, V T is the thermal voltage, and n is a constant. It was shown in[78] that leakage variations for 90nm can be 20 ×. Based on the ITRS[71], the leakage power accounts for more than 60% at 45nm; there are many consequences for chip design, especially for design of the power grid.
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Shen, R., Tan, S.XD., Yu, H. (2012). Statistical Power Grid Analysis Considering Log-Normal Leakage Current Variations. In: Statistical Performance Analysis and Modeling Techniques for Nanometer VLSI Designs. Springer, Boston, MA. https://doi.org/10.1007/978-1-4614-0788-1_8
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