Abstract
It is well accepted that the process-induced variability has huge impacts on the circuit performance in the sub-90 nm VLSI technologies. The variational consideration of process has to be assessed in various VLSI design steps to ensure robust circuit design. Process variations consist of both inter-die ones, which affect all the devices on the same chip in the same way, and intra-die ones, which represent variations of parameters within the same chip. These include spatially correlated variations and purely independent or uncorrelated variations. Spatial correlation describes the phenomenon that devices close to each other are more likely to have similar characteristics than when they are far apart. It was shown that variations in the practical chips in nanometer range are spatially correlated [195]. Simple assumption of independence for involved random variables can lead to significant errors.
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Shen, R., Tan, S.XD., Yu, H. (2012). Statistical Dynamic Power Estimation Techniques. In: Statistical Performance Analysis and Modeling Techniques for Nanometer VLSI Designs. Springer, Boston, MA. https://doi.org/10.1007/978-1-4614-0788-1_6
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