Skip to main content

Linear Statistical Leakage Analysis by Virtual Grid-Based Modeling

  • Chapter
  • First Online:
Statistical Performance Analysis and Modeling Techniques for Nanometer VLSI Designs

Abstract

When the spatial correlation is weak, existing general approaches mentioned in Chaps. 3 and 4 do not work well as the number of correlated variables cannot be reduced too much. Recently, an efficient method was proposed [200] to address this problem. The method is based on simplified gate leakage models and formulates the major computation tasks into matrix–vector multiplications via Taylor’s expansion. It then applies fast numerical methods like the fast multipole method or the precorrected fast Fourier transformation (FFT) method to compute the multiplication. However, this method assumes the gate-level leakage currents are purely log-normal, and the chip-level leakage is also approximated by log-normal distribution, which is not the case as we will show in the chapter. Also it can only give the mean and variances, not the complete distribution of the leakage powers.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

eBook
USD 16.99
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 129.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD 109.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

References

  1. A. Abdollahi, F. Fallah, and M. Pedram, “Runtime mechanisms for leakage current reduction in CMOS VLSI circuits,” in Proc. Int. Symp. on Low Power Electronics and Design (ISLPED), Aug 2002, pp. 213–218.

    Google Scholar 

  2. H. Chang and S. S. Sapatnekar, “Full-chip analysis of leakage power under process variations, including spatial correlations,” in Proc. IEEE/ACM Design Automation Conference (DAC), 2005, pp. 523–528.

    Google Scholar 

  3. R. Chen, L. Zhang, V. Zolotov, C. Visweswariah, and J. Xiong, “Static timing: back to our roots,” in Proc. Asia South Pacific Design Automation Conf. (ASPDAC), Jan 2008, pp. 310–315.

    Google Scholar 

  4. R. Fernandes and R. Vemuri, “Accurate estimation of vector dependent leakage power in presence of process variations,” in Proc. IEEE Int. Conf. on Computer Design (ICCD), Oct 2009, pp. 451–458.

    Google Scholar 

  5. R. G. Ghanem and P. D. Spanos, Stochastic Finite Elements: A Spectral Approach. Dover Publications, 2003.

    Google Scholar 

  6. K. R. Heloue, N. Azizi, and F. N. Najm, “Modeling and estimation of full-chip leakage current considering within-die correlation,” in Proc. IEEE/ACM Design Automation Conference (DAC), 2007, pp. 93–98.

    Google Scholar 

  7. “International technology roadmap for semiconductors (ITRS), 2010 update,” 2010, http://public.itrs.net.

  8. H. Jiang, M. Marek-Sadowska, and S. R. Nassif, “Benefits and costs of power-gating technique,” in Proc. IEEE Int. Conf. on Computer Design (ICCD), Oct 2005, pp. 559–566.

    Google Scholar 

  9. Y. Lin and D. Sylvester, “Runtimie lekaage power estimation technique for combinational circuits,” in Proc. Asia South Pacific Design Automation Conf. (ASPDAC), Jan 2007, pp. 660–665.

    Google Scholar 

  10. “MCNC benchmark circuit placements,” http://vlsicad.ucsd.edu/GSRC/bookshelf/Slots/~~Placement/.

  11. “Nangate open cell library,” http://www.nangate.com/.

  12. “Predictive Technology Model,” http://www.eas.asu.edu/~ptm/.

  13. R. Shen, N. Mi, S. X.-D. Tan, Y. Cai, and X. Hong, “Statistical modeling and analysis of chip-level leakage power by spectral stochastic method,” in Proc. Asia South Pacific Design Automation Conf. (ASPDAC), Jan 2009, pp. 161–166.

    Google Scholar 

  14. R. Shen, S. X.-D. Tan, and J. Xiong, “A linear algorithm for full-chip statistical leakage power analysis considering weak spatial correlation,” in Proc. Design Automation Conf. (DAC), Jun. 2010, pp. 481–486.

    Google Scholar 

  15. R. Shen, S. X.-D. Tan, and J. Xiong, “A linear statistical analysis for full-chip leakage power with spatial correlation,” in Proc. IEEE/ACM International Great Lakes Symposium on VLSI (GLSVLSI), May 2010, pp. 227–232.

    Google Scholar 

  16. H. Xu, R. Vemuri, and W. Jone, “Run-time active leakage reduction by power gating and reverse body biasing: An energy view,” in Proc. IEEE Int. Conf. on Computer Design (ICCD), Oct 2008, pp. 618–625.

    Google Scholar 

  17. Z. Ye and Z. Yu, “An efficient algorithm for modeling spatially-correlated process variation in statistical full-chip leakage analysis,” in Proc. Int. Conf. on Computer Aided Design (ICCAD), Nov 2009, pp. 295–301.

    Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Rights and permissions

Reprints and permissions

Copyright information

© 2012 Springer Science+Business Media, LLC

About this chapter

Cite this chapter

Shen, R., Tan, S.XD., Yu, H. (2012). Linear Statistical Leakage Analysis by Virtual Grid-Based Modeling. In: Statistical Performance Analysis and Modeling Techniques for Nanometer VLSI Designs. Springer, Boston, MA. https://doi.org/10.1007/978-1-4614-0788-1_5

Download citation

  • DOI: https://doi.org/10.1007/978-1-4614-0788-1_5

  • Published:

  • Publisher Name: Springer, Boston, MA

  • Print ISBN: 978-1-4614-0787-4

  • Online ISBN: 978-1-4614-0788-1

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics