Abstract
In this chapter, we present a gate-based general full-chip leakage modeling and analysis method [157]. The gate-based method starts with the process variational parameters such as the channel length, δL, and gate oxide thickness, δT ox, and it can derive the full-chip leakage current I leak in terms of those variables directly (or their corresponding transformed variables). Unlike existing grid-based methods, which trade the accuracy for speedup, the presented method is gate-based method and uses principal component analysis (PCA) to reduce the number of variables with much less accuracy loss, assuming that the geometrical variables are Gaussian. For non-Gaussian variables, independent component analysis (ICA) [68] can be used. The presented method considers both inter-die and intra-die variations, and it can work with various spatial correlations. The presented method becomes linear under strong spatial correlations. Unlike the existing approaches [13, 65], the presented method does not make any assumptions about the distributions of final total leakage currents for both gates and chips and does not require any grid-based partitioning of the chip. Compared with [5], the presented method applies a more efficient multidimensional numerical quadrature method (vs. reduced number of variables using interproduction via the moment matching), considers more accurate leakage models, and presents more comprehensive comparisons with other methods.
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Shen, R., Tan, S.XD., Yu, H. (2012). Statistical Leakage Power Analysis by Spectral Stochastic Method. In: Statistical Performance Analysis and Modeling Techniques for Nanometer VLSI Designs. Springer, Boston, MA. https://doi.org/10.1007/978-1-4614-0788-1_4
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DOI: https://doi.org/10.1007/978-1-4614-0788-1_4
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