Skip to main content

Abstract

In this chapter, we present a gate-based general full-chip leakage modeling and analysis method [157]. The gate-based method starts with the process variational parameters such as the channel length, δL, and gate oxide thickness, δT ox, and it can derive the full-chip leakage current I leak in terms of those variables directly (or their corresponding transformed variables). Unlike existing grid-based methods, which trade the accuracy for speedup, the presented method is gate-based method and uses principal component analysis (PCA) to reduce the number of variables with much less accuracy loss, assuming that the geometrical variables are Gaussian. For non-Gaussian variables, independent component analysis (ICA) [68] can be used. The presented method considers both inter-die and intra-die variations, and it can work with various spatial correlations. The presented method becomes linear under strong spatial correlations. Unlike the existing approaches [13, 65], the presented method does not make any assumptions about the distributions of final total leakage currents for both gates and chips and does not require any grid-based partitioning of the chip. Compared with [5], the presented method applies a more efficient multidimensional numerical quadrature method (vs. reduced number of variables using interproduction via the moment matching), considers more accurate leakage models, and presents more comprehensive comparisons with other methods.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

eBook
USD 16.99
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 129.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD 109.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

References

  1. S. Bhardwaj, S. Vrudhula, and A. Goel, “A unified approach for full chip statistical timing and leakage analysis of nanoscale circuits considering intradie process variations,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 27, no. 10, pp. 1812–1825, Oct 2008.

    Article  Google Scholar 

  2. H. Chang and S. S. Sapatnekar, “Full-chip analysis of leakage power under process variations, including spatial correlations,” in Proc. IEEE/ACM Design Automation Conference (DAC), 2005, pp. 523–528.

    Google Scholar 

  3. R. G. Ghanem and P. D. Spanos, Stochastic Finite Elements: A Spectral Approach. Dover Publications, 2003.

    Google Scholar 

  4. K. R. Heloue, N. Azizi, and F. N. Najm, “Modeling and estimation of full-chip leakage current considering within-die correlation,” in Proc. IEEE/ACM Design Automation Conference (DAC), 2007, pp. 93–98.

    Google Scholar 

  5. A. Hyvarinen, J. Karhunen, and E. Oja, Independent Component Analysis. Wiley, 2001.

    Google Scholar 

  6. “MCNC benchmark circuit placements,” http://vlsicad.ucsd.edu/GSRC/bookshelf/Slots/%5CPlacement/.

  7. “Predictive Technology Model,” http://www.eas.asu.edu/~ptm/.

  8. R. Shen, N. Mi, S. X.-D. Tan, Y. Cai, and X. Hong, “Statistical modeling and analysis of chip-level leakage power by spectral stochastic method,” in Proc. Asia South Pacific Design Automation Conf. (ASPDAC), Jan 2009, pp. 161–166.

    Google Scholar 

  9. R. Shen, S. X.-D. Tan, N. Mi, and Y. Cai, “Statistical modeling and analysis of chip-level leakage power by spectral stochastic method,” Integration, the VLSI Journal, vol. 43, no. 1, pp. 156–165, January 2010.

    Article  Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Rights and permissions

Reprints and permissions

Copyright information

© 2012 Springer Science+Business Media, LLC

About this chapter

Cite this chapter

Shen, R., Tan, S.XD., Yu, H. (2012). Statistical Leakage Power Analysis by Spectral Stochastic Method. In: Statistical Performance Analysis and Modeling Techniques for Nanometer VLSI Designs. Springer, Boston, MA. https://doi.org/10.1007/978-1-4614-0788-1_4

Download citation

  • DOI: https://doi.org/10.1007/978-1-4614-0788-1_4

  • Published:

  • Publisher Name: Springer, Boston, MA

  • Print ISBN: 978-1-4614-0787-4

  • Online ISBN: 978-1-4614-0788-1

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics