Abstract
Process-induced variability has huge impact on the circuit performance in the sub-90 nm VLSI technologies [120]. This is the particular case for leakage power, which has increased dramatically with the technology scaling and is becoming the dominant chip power dissipation [71].
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Shen, R., Tan, S.XD., Yu, H. (2012). Traditional Statistical Leakage Power Analysis Methods. In: Statistical Performance Analysis and Modeling Techniques for Nanometer VLSI Designs. Springer, Boston, MA. https://doi.org/10.1007/978-1-4614-0788-1_3
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