Abstract
A significant portion of process variations are purely random in nature [122]. As a result, variation-aware design methodologies and statistical computer-aided design (CAD) tools are widely believed to be the key to mitigating some of the challenges for 45 nm technologies and beyond [148, 122]. Variational considerations have to be incorporated into every step of the design and verification processes to ensure reliable chips and profitable manufacturing yields.
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References
Z. Hao, S. X.-D. Tan, E. Tlelo-Cuautle, J. Relles, C. Hu, W. Yu, Y. Cai, and G. Shi, “Statistical extraction and modeling of inductance considering spatial correlation,” Analog Integr Circ Sig Process, 2012, in press.
R. Jiang, W. Fu, J. M. Wang, V. Lin, and C. C.-P. Chen, “Efficient statistical capacitance variability modeling with orthogonal principle factor analysis,” in Proc. Int. Conf. on Computer Aided Design (ICCAD), 2005, pp. 683–690.
M. Kamon, M. Tsuk, and J. White, “FastHenry: a multipole-accelerated 3D inductance extraction program,” IEEE Trans. on Microwave Theory and Techniques, pp. 1750–1758, Sept. 1994.
K. Narbos and J. White, “FastCap: a multipole accelerated 3D capacitance extraction program,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 10, no. 11, pp. 1447–1459, 1991.
S. R. Nassif, “Model to hardware correlation for nm-scale technologies,” in Proc. IEEE International Workshop on Behavioral Modeling and Simulation (BMAS), Sept 2007, keynote speech.
J. Relles, M. Ngan, E. Tlelo-Cuautle, S. X.-D. Tan, C. Hu, W. Yu, and Y. Cai, “Statistical extraction and modeling of 3D inductance with spatial correlation,” in Proc. IEEE International Workshop on Symbolic and Numerical Methods, Modeling and Applications to Circuit Design, Oct 2010.
A. E. Ruehli, “Equivalent circuits models for three dimensional multiconductor systems,” IEEE Trans. on Microwave Theory and Techniques, pp. 216–220, 1974.
R. Rutenbar, “Next-generation design and EDA challenges,” in Proc. Asia South Pacific Design Automation Conf. (ASPDAC), January 2007, keynote speech.
W. Yu, C. Hu, and W. Zhang, “Variational capacitance extraction of on-chip interconnects based on continuous surface model,” in Proc. IEEE/ACM Design Automation Conference (DAC), July 2009, pp. 758–763.
Y. Zhou, Z. Li, Y. Tian, W. Shi, and F. Liu, “A new methodology for interconnect parasitics extraction considering photo-lithography effects,” in Proc. Asia South Pacific Design Automation Conf. (ASPDAC), Jan 2007, pp. 450–455.
H. Zhu, X. Zeng, W. Cai, J. Xue, and D. Zhou, “A sparse grid based spectral stochastic collocation method for variations-aware capacitance extraction of interconnects under nanometer process technology,” in Proc. Design, Automation and Test In Europe. (DATE), Mar 2007, pp. 1514–1519.
Z. Zhu and J. White, “FastSies: a fast stochastic integral equation solver for modeling the rough surface effect,” in Proc. Int. Conf. on Computer Aided Design (ICCAD), 2005, pp. 675–682.
Z. Zhu, B. Song, and J. White, “Algorithms in FastImp: a fast and wideband impedance extraction program for complicated 3-d geometries,” in Proc. Design Automation Conf. (DAC). New York, NY, USA: ACM, 2003, pp. 712–717.
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Shen, R., Tan, S.XD., Yu, H. (2012). Statistical Inductance Modeling and Extraction. In: Statistical Performance Analysis and Modeling Techniques for Nanometer VLSI Designs. Springer, Boston, MA. https://doi.org/10.1007/978-1-4614-0788-1_13
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DOI: https://doi.org/10.1007/978-1-4614-0788-1_13
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