Abstract
Since the interconnect length and cross area are at different scales, the variational capacitance extraction is quite different between the on-chip[209, 205, 21] and the off-chip[210, 34]. The on-chip interconnect variation from the geometrical parameters, such as width length of one panel and distance between two panels, is more dominant[209, 21] than the rough surface effect seen from the off-chip package trace. However, it is unknown how to leverage the stochastic process variation into the matrix-vector product (MVP) by fast multipole method (FMM)[210, 209, 205, 21, 34]. Similar to deal with the stochastic analog mismatch for transistors[133], a cost-efficient full-chip extraction needs to explore an explicit relation between the stochastic variation and the geometrical parameter such that the electrical property can show an explicit dependence on geometrical parameters. Moreover, the expansion by OPC with different collocation schemes[196, 187, 209, 21, 34] always results in an augmented and dense system equation. This significantly increases the complexity when dealing with a large-scale problem. The according GMRES thereby needs to be designed in an incremental fashion to consider the update from the process variation. As a result, a scalable extraction algorithm similar to [118, 77, 163] is required to consider the process variation with the new MVP and GMRES developed accordingly as well.
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Shen, R., Tan, S.XD., Yu, H. (2012). Incremental Extraction of Variational Capacitance. In: Statistical Performance Analysis and Modeling Techniques for Nanometer VLSI Designs. Springer, Boston, MA. https://doi.org/10.1007/978-1-4614-0788-1_12
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