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Statistical Capacitance Modeling and Extraction

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Statistical Performance Analysis and Modeling Techniques for Nanometer VLSI Designs

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Abstract

It is well accepted that the process-induced variability has huge impacts on the circuit performance in the sub-100 nm VLSI technologies [121, 120]. The variational consideration of process has to be assessed in various VLSI design steps to ensure robust circuit design. Process variations consist of both systematic ones, which depend on patterns and other process parameters, and random ones, which have to be dealt with using stochastic approaches. Efficient capacitance extraction approaches by using the boundary element method (BEM) such as the fastCap[115], HiCap [164], and PHiCap [199] have been proposed in the past. To consider the variation impacts on the interconnects, one has to consider the RLC extraction processes of the three-dimensional structures modeling the interconnect conductors. In this chapter, we investigate the geometry variational impacts on the extracted capacitance.

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Notes

  1. 1.

    Note that the scale factor 1 ∕ (4πε0) can be ignored here to simplify the notation and is used in the implementation to give results in units of farads.

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Authors and Affiliations

  1. Department of Electrical Engineering, University of California, Riverside, USA

    Ruijing Shen & Sheldon X.-D. Tan

  2. Department of Electrical and Electronic, Nanyang Technological University, Nanyang Avenue 50, Singapore, Singapore

    Hao Yu

Authors
  1. Ruijing Shen
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  2. Sheldon X.-D. Tan
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  3. Hao Yu
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Shen, R., Tan, S.XD., Yu, H. (2012). Statistical Capacitance Modeling and Extraction. In: Statistical Performance Analysis and Modeling Techniques for Nanometer VLSI Designs. Springer, Boston, MA. https://doi.org/10.1007/978-1-4614-0788-1_11

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  • DOI: https://doi.org/10.1007/978-1-4614-0788-1_11

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