Abstract
As VLSI technology scales into the nanometer regime, chip design engineering faces several challenges in maintaining historical rates of performance improvement and capacity increase with CMOS technologies. One profound change in the chip design business is that engineers cannot put the design precisely into the silicon chips. Chip performance, manufacture yield, and lifetime become unpredictable at the design stage, and they cannot be determined accurately at the design stage. The main culprit is that many chip parameters—such as oxide thickness due to chemical and mechanical polish (CMP) and impurity density from doping fluctuations—cannot be determined precisely and thus are unpredictable. The so-called manufacture process variations start to play a big role, and their influence on the chip’s performance, yield, and reliability becomes significant [16, 7, 170, 121, 122].
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
S. Borkar, T. Karnik, and V. De, “Design and reliability challenges in nanometer technologies,” in Proc. Design Automation Conf. (DAC). IEEE Press, 2004, pp. 75–75.
S. Borkar, T. Karnik, S. Narendra, J. Tschanz, A. Keshavarzi, and V. De, “Parameter variations and impact on circuits and microarchitecture,” in Proc. Design Automation Conf. (DAC). IEEE Press, 2003, pp. 338–342.
H. Chang and S. S. Sapatnekar, “Full-chip analysis of leakage power under process variations, including spatial correlations,” in Proc. IEEE/ACM Design Automation Conference (DAC), 2005, pp. 523–528.
C. Chiang and J. Kawa, Design for Manufacturability. Springer, 2007.
P. Friedberg, Y. Cao, J. Cain, R. Wang, J. Rabaey, and C. Spanos, “Modeling within-die spatial correlation effects for process design co-optimization,” in Proceedings of the 6th International Symposium on Quality of Electronic Design, 2005, pp. 516–521.
Z. Hao, R. Shen, S. X.-D. Tan, B. Liu, G. Shi, and Y. Cai, “Statistical full-chip dynamic power estimation considering spatial correlations,” in Proc. Int. Symposium. on Quality Electronic Design (ISQED), March 2011, pp. 677–782.
Z. Hao, S. X.-D. Tan, and G. Shi, “An efficient statistical chip-level total power estimation method considering process variations with spatial correlation,” in Proc. Int. Symposium. on Quality Electronic Design (ISQED), March 2011, pp. 671–676.
T. Karnik, S. Borkar, and V. De, “Sub-90 nm technologies-challenges and opportunities for CAD,” in Proc. Int. Conf. on Computer Aided Design (ICCAD), San Jose, CA, Nov 2002, pp. 203–206.
P. Li and W. Shi, “Model order reduction of linear networks with massive ports via frequency-dependent port packing,” in Proc. Design Automation Conf. (DAC), 2006, pp. 267–272.
Y. Liu, S. Nassif, L. Pileggi, and A. Strojwas, “Impact of interconnect variations on the clock skew of a gigahertz microprocessor,” in Proc. IEEE/ACM Design Automation Conference (DAC), 2000, pp. 168–171.
S. Nassif, “Design for variability in DSM technologies,” in Proc. Int. Symposium. on Quality Electronic Design (ISQED), San Jose, CA, Mar 2000, pp. 451–454.
S. R. Nassif, “Model to hardware correlation for nm-scale technologies,” in Proc. IEEE International Workshop on Behavioral Modeling and Simulation (BMAS), Sept 2007, keynote speech.
M. Orshansky, L. Milor, and C. Hu, “Characterization of spatial intrafield gate cd variability, its impact on circuit performance, and spatial mask-level correction,” in IEEE Trans. on Semiconductor Devices, vol. 17, no. 1, Feb 2004, pp. 2–11.
S. B. Samaan, “The impact of device parameter variations on the frequency and performance of VLSI chips,” in Proc. Int. Conf. on Computer Aided Design (ICCAD), ser. ICCAD ’04, 2004, pp. 343–346.
A. Srivastava, D. Sylvester, and D. Blaauw, Statistical Analysis and Optimization for VLSI: Timing and Power. Springer, 2005.
J. Xiong, V. Zolotov, and L. He, “Robust extraction of spatial correlation,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 26, no. 4, 2007.
Author information
Authors and Affiliations
Rights and permissions
Copyright information
© 2012 Springer Science+Business Media, LLC
About this chapter
Cite this chapter
Shen, R., Tan, S.XD., Yu, H. (2012). Introduction. In: Statistical Performance Analysis and Modeling Techniques for Nanometer VLSI Designs. Springer, Boston, MA. https://doi.org/10.1007/978-1-4614-0788-1_1
Download citation
DOI: https://doi.org/10.1007/978-1-4614-0788-1_1
Published:
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4614-0787-4
Online ISBN: 978-1-4614-0788-1
eBook Packages: EngineeringEngineering (R0)