Abstract
In Chapter 4 you learned how to connect the design and testbench with interfaces. These physical interfaces represent real signals, similar to the wires that connected ports in Verilog-1995. A testbench uses these interfaces by statically connecting to them through ports. However, for many designs, the testbench needs to connect dynamically to the design.
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© 2012 Springer Science+Business Media, LLC
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Spear, C., Tumbush, G. (2012). Advanced Interfaces. In: SystemVerilog for Verification. Springer, Boston, MA. https://doi.org/10.1007/978-1-4614-0715-7_10
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DOI: https://doi.org/10.1007/978-1-4614-0715-7_10
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Publisher Name: Springer, Boston, MA
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Online ISBN: 978-1-4614-0715-7
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