Abstract
In this chapter, we study an efficient and accurate full-chip through-silicon-via (TSV) interfacial crack analysis flow and design optimization methodology to alleviate TSV interfacial crack problems in 3D ICs. First, we analyze the TSV interfacial crack at the TSV/dielectric liner interface caused by TSV-induced thermo-mechanical stress. Then, we explore the impact of TSV placement in conjunction with various associated structures such as a landing pad and a dielectric liner on the TSV interfacial crack. Next, we study a full-chip TSV interfacial crack analysis methodology based on design of experiments (DOE) and response surface method (RSM). Finally, we study design optimization methodologies to mitigate the mechanical reliability problems in 3D ICs.
The materials presented in this chapter are based on [2].
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References
G.V. der Plas et al., Design issues and considerations for low-cost 3D TSV IC technology, in IEEE International Solid-State Circuits Conference Digest Technical Papers, San Francisco, (IEEE, Piscataway, 2010)
M. Jung, X. Liu, S.K. Sitaraman, D.Z. Pan, S.K. Lim, Full-chip through-silicon-via interfacial crack analysis and optimization for 3D IC, in Proceedings of IEEE International Conference on Computer-Aided Design, San Jose, 2011
A.P. Karmarkar, X. Xu, V. Moroz, Performance and reliability analysis of 3D-integration structures employing through silicon via (TSV), in IEEE International Reliability Physics Symposium, Montreal, (IEEE, New York/Piscataway, 2009)
D.H. Kim, K. Athikulwongse, S.K. Lim, A study of through-silicon-via impact on the 3D stacked IC layout, in Proceedings of IEEE International Conference on Computer-Aided Design, San Jose, (ACM, New York, 2009)
Y.-J. Lee, R. Goel, S.K. Lim, Multi-functional interconnect co-optimization for fast and reliable 3D stacked ICs, in Proceedings of IEEE International Conference on Computer-Aided Design, San Jose, (ACM, New York, 2009)
X. Liu, Q. Chen, P. Dixit, R. Chatterjee, R.R. Tummala, S.K. Sitaraman, Failure mechanisms and optimum design for electroplated copper through-silicon vias (TSV), in IEEE Electronic Components and Technology Conference, San Diego, (IEEE, Piscataway, 2009)
K.H. Lu, X. Zhang, S.-K. Ryu, J. Im, R. Huang, P.S. Ho, Thermo-mechanical reliability of 3-D ICs containing through silicon vias, in IEEE Electronic Components and Technology Conference, San Diego, (IEEE, Piscataway, 2009)
K.H. Lu, S.-K. Ryu, Q. Zhao, X. Zhang, J. Im, R. Huang, P.S. Ho, Thermal stress induced delamination of through silicon vias in 3-D interconnects, in IEEE Electronic Components and Technology Conference, Las Vegas, (IEEE, Piscataway, 2010)
S.-K. Ryu, K.-H. Lu, X. Zhang, J.-H. Im, P.S. Ho, R. Huang, Impact of near-surface thermal stresses on interfacial reliability of through-silicon-vias for 3-D interconnects. IEEE Trans. Device Mater. Reliab. 11, 35–43 (2011)
J.-S. Yang, K. Athikulwongse, Y.-J. Lee, S.K. Lim, D.Z. Pan, TSV stress aware timing analysis with applications to 3D-IC layout optimization, in Proceedings of ACM Design Automation Conference, anaheim, (ACM, New York, 2010)
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Lim, S.K. (2013). TSV Interfacial Crack Analysis and Optimization. In: Design for High Performance, Low Power, and Reliable 3D Integrated Circuits. Springer, New York, NY. https://doi.org/10.1007/978-1-4419-9542-1_17
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DOI: https://doi.org/10.1007/978-1-4419-9542-1_17
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