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Side-Channel Attacks and Countermeasures for Embedded Microcontrollers

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Introduction to Hardware Security and Trust

Abstract

While trustworthy hardware helps to establish the basis of trustworthy computing, most applications in embedded security rely to a significant extent on software. Smart-cards are an excellent example. A smart-card is an embedded computer in the form factor of a credit card with an integrated microcontroller. In contrast to a credit card, a smart-card thus has an active component. This allows the card to execute one side of a cryptographic protocol, such as digital signature-generation. Crypto-protocols are build using crypto-algorithms including symmetric-key and public-key encryption, random number generation, and hashing. A smart-card may implement these building blocks in software or, in some cases, in dedicated hardware. Software is often preferred because of two different reasons: reducing the design cost and supporting flexibility. This chapter will discuss the implementation of side-channel attacks on such microcontrollers, as well as some common countermeasures. The objective is to introduce the reader to this exciting field of research within the limits of a book chapter. In-depth discussion of side-channel analysis on microcontrollers can be found in the literature, e.g., [1].

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References

  1. Mangard S, Oswald E, Popp T (2007) Power Analysis Attacks: Revealing the Secrets of Smart Cards. Springer, Berlin

    MATH  Google Scholar 

  2. Prouff E, Rivain M (2009) Theoretical and practical aspects of mutual information based side channel analysis. In: ACNS’09: Proceedings of the 7th International Conference on Applied Cryptography and Network Security, Springer-Verlag, Berlin, pp 499–518

    Google Scholar 

  3. Kocher PC, Jaffe J, Jun B (1999) Differential power analysis. In: CRYPTO, pp 388–397

    Google Scholar 

  4. Brier E, Clavier C, Olivier F (2004) Correlation power analysis with a leakage model. In: CHES, pp 16–29

    Google Scholar 

  5. Archambeau C, Peeters E, Standaert F-X, Quisquater J-J (2006) Template attacks in principal subspaces. In: CHES, pp 1–14

    Google Scholar 

  6. Chari S, Rao JR, Rohatgi P (2003) Template attacks. In: CHES’02: 4th International Workshop on Cryptographic Hardware and Embedded Systems, Springer, London, UK, pp 13–28

    Google Scholar 

  7. Rechberger C, Oswald E (2004) Practical template attacks. In: WISA, pp 440–456

    Google Scholar 

  8. Daemen J, Rijmen V (2002) The Design of Rijndael. Secaucus, NJ, USA: Springer, New York, Inc.

    MATH  Google Scholar 

  9. Akkar M-L, Giraud C (2001) An implementation of DES and AES, secure against some attacks. In: CHES 2001, vol LNCS 2162, pp 309–318

    Google Scholar 

  10. Oswald E, Schramm K (2005) An efficient masking scheme for AES software implementations. In: WISA 2005, vol LNCS 3786, pp 292–305

    Google Scholar 

  11. Gebotys CH (2006) A split-mask countermeasure for low-energy secure embedded systems. ACM Trans Embed Comput Syst 5(3): 577–612

    Article  Google Scholar 

  12. Ambrose JA, Ragel RG, Parameswaran S (2007) rijid: Random code injection to mask power analysis based side channel attacks. In: DAC 2007, pp 489–492

    Google Scholar 

  13. Clavier C, Coron J-S, Dabbous N (2000) Differential power analysis in the presence of hardware countermeasures. In: CHES 2000, vol LNCS 1965, pp 252–263

    Google Scholar 

  14. Schaumont P, Tiri K (2007) Masking and dual-rail logic don’t add up. In: Cryptographic hardware and embedded systems (CHES 2007), vol 4727 of Lecture Notes on Computer Science. Springer, Berlin, Heidelberg, New York, pp 95–106

    Google Scholar 

  15. Tiri K, Verbauwhede I (2004) A logic level design methodology for a secure DPA resistant ASIC or FPGA implementation. In: Proceedings of the Design, Automation and Test in Europe Conference and Exhibition, 2004, vol 1, pp 246–251, February 2004

    Google Scholar 

  16. Popp T, Mangard S (2007) Masked dual-rail pre-charge logic: DPA resistance without the routing constraints. In: Cryptographic Hardware and Embedded Systems – CHES 2007, vol 4727. Springer, Berlin, Heidelberg, New York, pp 81–94

    Google Scholar 

  17. Suzuki D, Saeki M, Ichikawa T (2007) Random switching logic: a new countermeasure against DPA and second-order DPA at the logic level. IEICE Trans 90-A(1): 160–168

    Google Scholar 

  18. Popp T, Kirschbaum M, Zefferer T, Mangard S (2007) Evaluation of the masked logic style MDPL on a prototype chip. In: CHES’07: Proceedings of the 9th international workshop on Cryptographic Hardware and Embedded Systems. Springer, Berlin, Heidelberg, New York, pp 81–94

    Google Scholar 

  19. Chen Z, Sinha A, Schaumont P (2010) Implementing virtual secure circuit using a custom-instruction approach. In: Proceedings of the 2010 international conference on Compilers, architectures and synthesis for embedded systems, CASES’10. ACM, New York, NY, USA, pp 57–66

    Google Scholar 

  20. Chen Z, Schaumont P (2010) Virtual secure circuit: porting dual-rail pre-charge technique into software on multicore. Cryptology ePrint Archive, Report 2010/272. http://eprint.iacr.org/

  21. Tiri K, Verbauwhede I (2003) Securing encryption algorithms against DPA at the logic level: next generation smart card. In: CHES 2003, vol LNCS 2779, pp 125–136

    Google Scholar 

  22. Tiri K, Verbauwhede I (2004) A logic level design methodology for a secure DPA resistant ASIC or FPGA implementation. In: Proceeding of DATE 2004, vol 1, pp 246–251

    Google Scholar 

  23. Popp T, Mangard S (2005) Masked dual-rail pre-charge logic: DPA-resistance without routing constraints. In: CHES 2005, vol LNCS 3659, pp 172–186

    Google Scholar 

  24. Biham E (1997) A fast new DES implementation in software. In: FSE’97: Proceedings of the 4th International Workshop on Fast Software Encryption. Springer, London, UK, pp 260–272

    Google Scholar 

  25. Konighofer R (2008) A fast and cache-timing resistant implementation of the AES. In: CT-RSA’08: Proceedings of the 2008 The Cryptopgraphers’ Track at the RSA conference on Topics in cryptology. Springer, Berlin, pp 187–202

    Google Scholar 

  26. Matsui M (2006) How far can we go on the x64 Processors? In: FSE, pp 341–358

    Google Scholar 

  27. Kasper E, Schwabe P (2009) Faster and timing-attack resistant AES-GCM. In: CHES, pp 1–17

    Google Scholar 

  28. Matsui M, Nakajima J (2007) On the power of bitslice implementation on Intel Core2 processor. In: CHES’07: Proceedings of the 9th International Workshop on Cryptographic Hardware and Embedded Systems. Springer, Berlin, Heidelberg, New York, pp 121–134

    Google Scholar 

  29. Rebeiro C, Selvakumar D, Devi A (2006) Bitslice implementation of AES. In: CANS, vol LNCS 4301, pp 203–212

    Google Scholar 

  30. Brier E, Clavier C, Olivier F (2004) Correlation power analysis with a leakage model. In: CHES 2004, vol LNCS 3156, pp 16–29

    Google Scholar 

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Authors and Affiliations

  1. ECE Department, Virginia Tech, Blacksburg, VA, 24061, USA

    Patrick Schaumont & Zhimin Chen

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  1. Patrick Schaumont
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  2. Zhimin Chen
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Correspondence to Patrick Schaumont .

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Editors and Affiliations

  1. , ECE Dept., University of Connecticut, Fairfield Way 371, Storrs, 06269, Connecticut, USA

    Mohammad Tehranipoor

  2. Computing and Information Science Div., Engineering Sciences Directorate, Triangle Park, 27709-2211, North Carolina, USA

    Cliff Wang

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Schaumont, P., Chen, Z. (2012). Side-Channel Attacks and Countermeasures for Embedded Microcontrollers. In: Tehranipoor, M., Wang, C. (eds) Introduction to Hardware Security and Trust. Springer, New York, NY. https://doi.org/10.1007/978-1-4419-8080-9_11

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  • DOI: https://doi.org/10.1007/978-1-4419-8080-9_11

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  • Print ISBN: 978-1-4419-8079-3

  • Online ISBN: 978-1-4419-8080-9

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