Abstract
To meet customer’s product-quality expectations, each individual IC needs to be tested for manufacturing defects incurred during its many high-precision, and hence defect-prone manufacturing steps; these tests should be both effective and cost-efficient. The semiconductor industry is preparing itself now for three-dimensional stacked ICs (3D-SICs) based on Through-Silicon Vias (TSVs), which, due to their many compelling benefits, are quickly gaining ground. Test solutions need to be ready for this new generation of ‘super chips’. 3D-SICs are chips where all basic, as well as most advanced test technologies come together. In addition, they pose some truly new test challenges with respect to complexity and cost, due to their advanced manufacturing processes and physical access limitations. This chapter focuses on the challenges of testing 3D-SICs, and describes for which challenges solutions are already available or emerging. It provides an overview of the manufacturing steps of TSV-based 3D-SICs, as far as relevant for testing. Subsequently, it discusses flows for wafer-level and package-level tests, the challenges with respect to test contents and wafer-level probe access, and the on-chip Design-for-Test (DfT) infrastructure required for 3D-SICs.
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Acknowledgments
We thank many colleagues at IMEC for stimulating discussions, especially Eric Beyne, Ingrid De Wolf, Luc Dupas, Mario Gonzalez, Anne Jourdain, Paresh Limaye, Pol Marchal, Nikolaos Minas, Dan Perry, Philippe Roussel, Geert Van der Plas, Bart Swinnen, Kris Vanstreels, Dimitrios Velenis, and Jouke Verbree.
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Marinissen, E. (2011). Testing 3D Stacked ICs Containing Through-Silicon Vias. In: Sheibanyrad, A., Pétrot, F., Jantsch, A. (eds) 3D Integration for NoC-based SoC Architectures. Integrated Circuits and Systems. Springer, New York, NY. https://doi.org/10.1007/978-1-4419-7618-5_3
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DOI: https://doi.org/10.1007/978-1-4419-7618-5_3
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