EJTAG and Trace in Toshiba TX Cores

Abstract

Toshiba supports debug using a version of EJTAG interface revision 1.5, which was released in the late 1990s. This diverges from the current MIPS-EJTAG interface revisions, so a MIPS EJTAG debugger to would not support Toshiba MIPS architecture based parts (and vica versa). Likewise, debug instruction and registers are different from current MIPS. Like other versions of EJTAG, the Toshiba EJTAG interface is an extension to the IEEE 1149.1 JTAG interface. Additional status pins and debug clock signals, in conjunction with JTAG pins, provide real-time PC trace information. Because serial bus access to the memory in the external processor probe is available through the JTAG interface, the debug program can be placed in the external memory. Access to all resources’ connected to the processor is available by the DMA function through JTAG interface. The debug support unit (DSU) in the Toshiba MIPS core has an 8-double-word scratch pad memory (MIB), which reduces communication time through JTAG interface.