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Fundamentals and Related Work

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Design of Image Processing Embedded Systems Using Multidimensional Data Flow

Part of the book series: Embedded Systems ((EMSY))

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Abstract

After having presented the challenges and requirements for system level design of image processing applications, this chapter aims to discuss fundamentals on system level design and to give an overview on related work. Section 3.1 starts with the question how to specify the application behavior. In this context also some fundamental data flow models of computation are reviewed. Next, Section 3.2 gives an introduction to existing approaches in behavioral hardware synthesis. Communication and memory synthesis techniques are discussed separately in Section 3.4. Section 3.3 details some aspects about memory analysis and optimization. Section 3.5 reviews several system-level design approaches before Section 3.6 concludes this chapter with a conclusion.

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Notes

  1. 1.

    Without break or continue statements.

  2. 2.

    A slight relaxation is possible by copying written data to several destinations.

  3. 3.

    Presence of deadlocks cannot be proved.

  4. 4.

    The split actor belongs to the class of CSDF, described in Section 3.1.3.2..

  5. 5.

    In [166], an alternative representation has been chosen in order to emphasize the behavior of a possible hardware implementation. As the latter is only able to read 1 pixel per clock cycle, the initial phase is split into several invocations. Furthermore, it has been assumed that the filter already reads the next input when processing the window at the right border.

  6. 6.

    now Thales

  7. 7.

    Note that this optimization differs from the JPEG2000 tiling described in Section 2.2 in that the latter introduces an additional border processing in order to avoid the resulting multiple data accesses. As such a behavior, however, changes the produced output result, it cannot be used automatically by the DEFACTO compiler.

  8. 8.

    A vector \(\mathbf{a}\in\mathbb{R}^{n}\) is called lexicographic positive if \(\exists i:\forall1\leq j < i,\,\langle\mathbf{a},\mathbf{e_{j}}\rangle\geq0\wedge\langle\mathbf{a},\mathbf{e_{i}}\rangle>0\).

  9. 9.

    The latter can be achieved by dividing the vector with the greatest common divisor of all vector components.

  10. 10.

    Note that in this case the execution semantics of the SDF graph slightly change because actor 2 has to check not only for sufficient input data, but also for enough free space on each output edge. From the theoretical point of view, however, this does not cause any difficulties since the occurring behavior can be modeled by introduction of a feedback edge between actors 3 and 2 [301].

  11. 11.

    It is assumed that the buffer has to be allocated at the beginning of the producing invocation and can be released at the end of the consuming invocation.

  12. 12.

    (see Section 3.2.4 for a mathematical definition)

  13. 13.

    This kind of loop programs indicate data dependencies instead of being supposed to execute all iterations sequentially.

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    Joachim Keinert

  2. Department of Computer Science 12, University of Erlangen-Nuremberg, Am Weichselgarten 3, D-91058, Erlangen, Germany

    Jürgen Teich

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Keinert, J., Teich, J. (2011). Fundamentals and Related Work. In: Design of Image Processing Embedded Systems Using Multidimensional Data Flow. Embedded Systems. Springer, New York, NY. https://doi.org/10.1007/978-1-4419-7182-1_3

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