Abstract
Properties play a central role in SVA because they form the bodies of concurrent assertions. A property is a temporal formula that can be either true or false on a given trace. An exception is disabled status of a property when the disable iff operator is used. See Sect. 13.1.1. As explained in Sect. 3.5.3, by trace we understand a series of all DUT signal values in time. Properties are interpreted over traces. In this chapter, we assume that each point on the trace corresponds to a tick of the clock on which the property is evaluated. This definition will not work for multiply clocked properties, but we currently limit our consideration to singly clocked properties only. The more general case is described in Chaps. 12, 13, and 20. Also, in formal verification (FV) we may assume that all the traces are infinite, which corresponds to the case when the property clock ticks infinitely many times. Of course, simulation traces are always finite. We informally describe the property semantics here, and defer the formal semantics of properties until Chap. 20.
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Notes
- 1.
An exception is disabled status of a property when the disable iff operator is used. See Sect. 13.1.1.
- 2.
Recall that according to our definition any integral expression is also a Boolean.
- 3.
This is further discussed in Chap. 8.
- 4.
See Chap. 14 for discussion about procedural concurrent assertions.
- 5.
Here, for convenience, we use the terms “property” and “assertion” interchangeably in the context of failure or success.
- 6.
As we explain in Chap. 8, since s_eventually is a strong operator, at the end of simulation when there are no more clock ticks and rst was high all the time, the simulator may declare failure of the property.
- 7.
Even though && is a short circuit operator (that is, its second operand is not evaluated if the first operand is evaluated to false), and and is not, there is no difference between them in this case, since expressions used in assertions cannot have side effects. See Sect. 4.1.
- 8.
The difference may not be observable in simulation depending on whether the simulator takes into account the strength of properties at the end of simulation. not e is a strong property, while !e is weak.
References
IEEE Standard for SystemVerilog Unified Hardware Design, Specification, and Verification Language (2005) IEEE Std 1800-2005, pp 1–648
Armoni R, Egorov S, Fraer R, Korchemny D, Vardi M (2005) Efficient LTL compilation for SAT-based model checking. In: ICCAD
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Cerny, E., Dudani, S., Havlicek, J., Korchemny, D. (2010). Basic Properties. In: The Power of Assertions in SystemVerilog. Springer, Boston, MA. https://doi.org/10.1007/978-1-4419-6600-1_4
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