Abstract
This chapter provides a brief introduction into SystemVerilog Assertions (SVA). The main concepts are explained on specific examples. We explain the peculiarities of the assertion language and its application in the contemporary design flow. The chapter discusses assertion kinds, assertion reuse and tools for assertion library support. The chapter is concluded with a brief comparison between PSL and SVA.
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Notes
- 1.
Until 2009 Verilog and SystemVerilog had separate standards. In 2009 both standards were merged into SystemVerilog standard.
- 2.
SystemVerilog also introduced many important object-oriented enhancements to Verilog, such as aggregate data types, classes, and interfaces [7].
- 3.
This example uses several SystemVerilog features not available in Verilog, e.g., logic data type (see Chap. 2 for more information).
- 4.
The reader may be used to the term “alwaysblock”, but according to the SystemVerilog 2009 standard, this construct is called alwaysprocedure”.
- 5.
This specification does not provide details about how the timeout condition is formed. Of course, a complete specification should provide them.
- 6.
Configurations were introduced in Verilog 2001 [2].
- 7.
Actually many verification tools do require some input information, such as a clock pattern or a reset sequence.
- 8.
Strictly speaking, true is not defined in SystemVerilog, but we will use it where appropriate as an alias for 1’b1. Similarly, we will use false for 1’b0.
- 9.
For simplicity, here and in future examples we ignore the possibility of unknown and high-impedance values X and Z unless explicitly stated.
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Cerny, E., Dudani, S., Havlicek, J., Korchemny, D. (2010). Introduction. In: The Power of Assertions in SystemVerilog. Springer, Boston, MA. https://doi.org/10.1007/978-1-4419-6600-1_1
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