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SCAMP-3: A Vision Chip with SIMD Current-Mode Analogue Processor Array

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Focal-Plane Sensor-Processor Chips

Abstract

In this chapter, the architecture, design and implementation of a vision chip with general-purpose programmable pixel-parallel cellular processor array, operating in single instruction multiple data (SIMD) mode is presented. The SIMD concurrent processor architecture is ideally suited to implementing low-level image processing algorithms. The datapath components (registers, I/O, arithmetic unit) of the processing elements of the array are built using switched-current circuits. The combination of a straightforward SIMD programming model, with digital microprocessor-like control and analogue datapath, produces an easy-to-use, flexible system, with high-degree of programmability, and efficient, low-power, small-footprint, circuit implementation. The SCAMP-3 chip integrates 128 ×128 pixel-processors and a flexible read-out circuitry, while the control system is fully digital, and currently implemented off-chip. The device implements low-level image processing algorithms on the focal plane, with a peak performance of more than 20 GOPS, and power consumption below 240mW.

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Acknowledgement

This work has been supported by the EPSRC; grant numbers: EP/D503213 and EP/D029759. The author thanks Dr Stephen Carey and Dr David Barr for their contributions to testing and system development for the SCAMP-3 device.

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Authors and Affiliations

  1. The University of Manchester, Manchester, M13 9PL, UK

    Piotr Dudek

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  1. Piotr Dudek
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Correspondence to Piotr Dudek .

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Editors and Affiliations

  1. Computer & Automation Research Inst., MTA Budapest, Budapest, 1518, Hungary

    Ákos Zarándy

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Dudek, P. (2011). SCAMP-3: A Vision Chip with SIMD Current-Mode Analogue Processor Array. In: Zarándy, Á. (eds) Focal-Plane Sensor-Processor Chips. Springer, New York, NY. https://doi.org/10.1007/978-1-4419-6475-5_2

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  • DOI: https://doi.org/10.1007/978-1-4419-6475-5_2

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