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Reconfigurable Networks-on-Chip

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Integrated Optical Interconnect Architectures for Embedded Systems

Part of the book series: Embedded Systems ((EMSY))

Abstract

There is little doubt that the most important limiting factors of the ­performance of next-generation chip multiprocessors (CMPs) will be the power efficiency and the available communication speed between cores. Photonic networks-on-chip (NoCs) have been suggested as a viable route to relieve the off- and on-chip interconnection bottleneck. Low-loss integrated optical waveguides can transport very high-speed data signals over longer distances as compared to on-chip electrical signaling. In addition, novel components such as silicon microrings, photonic switches and other reconfigurable elements can be integrated to route signals in a data-transparent way.

In this chapter, we look at the behavior of on-chip network traffic and show how the locality in space and time which it exhibits can be advantageously exploited by what we will define as “slowly reconfiguring” networks. We will review existing work on photonic reconfigurable NoCs, and provide implementation details and a performance and power characterization of our own reconfigurable photonic NoC proposal in which the topology is adapted automatically (on a microsecond scale) to the evolving traffic situation by use of silicon microrings.

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Notes

  1. 1.

    Or, in a message-passing system, processors can work on local data for a longer time before messages need to be sent with new data.

  2. 2.

    See [51] for the original description of Rent’s law relating the number of devices in a subset of an electronic circuit to its number of terminals, [14] for a theoretical derivation of the same law, and [23] for an extension of Rent’s rule which replaces the number of terminals with network bandwidth. In essence, a low Rent exponent (near zero) signifies very localized communication, such as nearest-neighbor only, while a very high Rent exponent (near one) denotes global, all-to-all communication.

  3. 3.

    Often, the operating system tries to avoid context switches at the same time on all nodes as this would initiate communication bursts on all nodes simultaneously, this can easily saturate the whole network.

  4. 4.

    One might consider using a larger cache line size to counter this, but an increase to multiple kilobyte would in most cases only result in excessive amounts of false sharing, negating any obtained performance increase.

  5. 5.

    Actually another set of VCs is used since separate request and reply VCs are already employed to avoid fetch deadlocks at the protocol level.

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Acknowledgements

This work was supported by the European Commission’s 6th FP Network of Excellence on Micro-Optics (NEMO), the BELSPO IAP P6/10 photonics@be network sponsored by the Belgian Science Policy Office, the GOA, the FWO, the OZR, the Methusalem and Hercules foundations. The work of C. Debaes is supported by the FWO (Fund for Scientic Research—Flanders) under a research fellowship.

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Authors and Affiliations

  1. Computer Systems Laboratory, Ghent University, Sint-Pietersnieuwstraat 41, Gent, 9000, Belgium

    Wim Heirman

  2. iTEAM, Universidad Politécnica de Valencia, Valencia, Spain

    Iñigo Artundo

  3. Department of Applied Physics and Photonics, Vrije Universiteit Brussel, Brussel, Belgium

    Christof Debaes

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  1. Wim Heirman
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  2. Iñigo Artundo
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Correspondence to Wim Heirman .

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  1. CNRS UMR 5270, Lyon Institute of Nanotechnology, Ecole Centrale de Lyon, av. Guy de Collongue 36, Ecully, 69134, France

    Ian O'Connor

  2. Dpt. Génie Informatique & Génie Logiciel, Ecole Polytechnique de Montreal, chemin de Polytechnique 2500, Montreal, H3T 1J4, Québec, Canada

    Gabriela Nicolescu

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Heirman, W., Artundo, I., Debaes, C. (2013). Reconfigurable Networks-on-Chip. In: O'Connor, I., Nicolescu, G. (eds) Integrated Optical Interconnect Architectures for Embedded Systems. Embedded Systems. Springer, New York, NY. https://doi.org/10.1007/978-1-4419-6193-8_7

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