Abstract
We outline an approach to verify pipelined machines with stuttering trace containment. Pipelined machines are complicated to reason about since they involve simultaneous overlapped execution of different instructions. Nevertheless, we show that if the logic used is sufficiently expressive, then it is possible to relate the executions of the pipelined machine with the corresponding Instruction Set Architecture using (stuttering) simulation. Our methodology uses first-order quantification to define a predicate that relates pipeline states with ISA states and uses its Skolem witness for correspondence proofs. Our methodology can be used to reason about generic pipelines with interrupts, stalls, and exceptions.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Notes
- 1.
Note that ma and ma 1F would possibly have different values of the program counter (PC). This is normally addressed by excluding the program counter from the labels of a state.
- 2.
Manolios also describes a “flushing proof” and shows that flushing can relate inconsistent MA states to ISA states. But our application of flush is different from his in that we flush ma 1 rather than the current state ma. In particular, our approach does not involve a refinement map constituting the flush of ma.
References
M. Aagaard, V. C. Ciubotariu, F. Khalvati, and J. T. Higgins. Combining Equivalence Verification and Completion Functions. In A. J. Hu and A. K. Martin, editors, Proceedings of the 5th International Conference on Formal Methods in Computer-Aided Design (FMCAD 2004), volume 3312 of LNCS, pages 98–112, Austin, TX, November 2004. Springer-Verlag.
M. Aagaard, B. Cook, N. Day, and R. B. Jones. A Framework for Microprocessor Correctness Statements. In T. Margaria and T. F. Melham, editors, Proceedings of the 11th International Conference on Correct Hardware Design and Verification Methods (CHARME 2001), volume 2144 of LNCS, pages 443–448, Scotland, UK, 2001. Springer-Verlag.
B. Brock and W. A. Hunt, Jr. Formal Analysis of the Motorola CAP DSP. In Industrial-Strength Formal Methods in Practice. Springer, 1999.
A. Bronstein and T. L. Talcott. Formal Verification of Pipelines Based on String-Functional Semantics. In L. J. M. Claesen, editor, Formal VLSI Correctness Verification, VLSI Design Methods II, pages 349–366, 1990.
R. E. Bryant, S. German, and M. N. Velev. Exploiting Positive Equality in a Logic of Equality with Uninterpreted Functions. In N. Halbwachs and D. Peled, editors, Proceedings of the 11th International Conference on Computer-Aided Verification (CAV 1999), volume 1633 of LNCS, pages 470–482, Trendo, Italy, 1999. Springer-Verlag.
R. E. Bryant, S. K. Lahiri, and S. A. Seshia. Modeling and Verifying Systems Using a Logic of Counter Arithmetic with Lambda Expressions and Uninterpreted Functions. In E. Brinksma and K. G. Larsen, editors, Proceedings of the 14th International Conference on Computer-Aided Verification (CAV 2002), volume 2404 of LNCS, pages 78–92, Copenhagen, Denmark, July 2002. Springer-Verlag.
J. R. Burch and D. L. Dill. Automatic Verification of Pipelined Microprocessor Control. In D. L. Dill, editor, Proceedings of the 6th International Conference on Computer-Aided Verification (CAV 1994), volume 818 of LNCS, pages 68–80, Stanford, CA, 1994. Springer-Verlag.
A. Cohn. A Proof of Correctness of the VIPER Microprocessor. Technical Report 104, University of Cambridge, Computer Laboratory, January 1987.
R. Hosabettu, G. Gopalakrishnan, and M. Srivas. Verifying Advanced Microarchitectures that Support Speculation and Exceptions. In E. A. Emerson and A. P. Sistla, editors, Proceedings of the 12th International Conference on Computer-Aided Verification (CAV 2000), volume 1855 of LNCS, Chicago, IL, July 2000. Springer-Verlag.
W. A. Hunt, Jr. FM8501: A Verified Microprocessor, volume 795 of LNAI. Springer-Verlag, 1994.
W. A. Hunt, Jr. and B. Brock. A Formal HDL and Its Use in the FM9001 Verification. In C. A. R. Hoare and M. J. C. Gordon, editors, Mechanized Reasoning and Hardware Design, Prentice-Hall International Series in Computer Science, pages 35–48, Englewood Cliffs, NJ, 1992. Prentice-Hall.
R. Jhala and K. McMillan. Microarchitecture Verification by Compositional Model Checking. In G. Berry, H. Comon, and A. Finkel, editors, Proceedings of 12th International Conference on Computer-Aided Verification (CAV), volume 2102 of LNCS, Paris, France, 2001. Springer-Verlag.
S. K. Lahiri and R. E. Bryant. Deductive Verification of Advanced Out-of-Order Microprocessors. In W. A. Hunt, Jr. and F. Somenzi, editors, Proceedings of the 15th International Conference on Computer-Aided Verification (CAV 2003), volume 2275 of LNCS, pages 341–354, Boulder, CO, July 2003. Springer-Verlag.
P. Manolios. Correctness of Pipelined Machines. In W. A. Hunt, Jr. and S. D. Johnson, editors, Proceedings of the 3rd International Conference on Formal Methods in Computer-Aided Design (FMCAD 2000), volume 1954 of LNCS, pages 161–178, Austin, TX, 2000. Springer-Verlag.
P. Manolios. A Compositional Theory of Refinement for Branching Time. In D. Geist, editor, Proceedings of the 12th Working Conference on Correct Hardware Design and Verification Methods, volume 2860 of LNCS, pages 304–218, L‘Aquila, Italy, 2003. Springer-Verlag.
P. Manolios and S. Srinivasan. Automatic Verification of Safety and Liveness of XScale-Like Processor Models Using WEB Refinements. In Design, Automation and Test in Europe (DATE 2004), pages 168–175, Paris, France, 2004. IEEE Computer Society Press.
P. Manolios and S. Srinivasan. Refinement Maps for Efficient Verification of Processor Models. In Design, Automation and Test in Europe (DATE 2005), pages 1304–1309, Munich, Germany, 2005. IEEE Computer Society Press.
S. Ray and W. A. Hunt, Jr. Deductive Verification of Pipelined Machines Using First-Order Quantification. In R. Alur and D. A. Peled, editors, Proceedings of the 16th International Conference on Computer-Aided Verification (CAV 2004), volume 3114 of LNCS, pages 31–43, Boston, MA, July 2004. Springer-Verlag.
J. Sawada. Verification of a Simple Pipelined Machine Model. In M. Kaufmann, P. Manolios, and J. S. Moore, editors, Computer-Aided Reasoning: ACL2 Case Studies, pages 35–53, Boston, MA, June 2000. Kluwer Academic Publishers.
J. Sawada and W. A. Hunt, Jr. Trace Table Based Approach for Pipelined Microprocessor Verification. In O. Grumberg, editor, Proceedings of the 9th International Conference on Computer-Aided Verification (CAV 1997), volume 1254 of LNCS, pages 364–375, Haifa, Israel, 1997. Springer-Verlag.
J. Sawada and W. A. Hunt, Jr. Processor Verification with Precise Exceptions and Speculative Execution. In A. J. Hu and M. Y. Vardi, editors, Proceedings of the 10th International Conference on Computer-Aided Verification (CAV 1998), volume 1427 of LNCS, pages 135–146, Vancouver, BC, 1998.Springer-Verlag.
J. Sawada and W. A. Hunt, Jr. Verification of FM9801: An Out-of-Order Microprocessor Model with Speculative Execution, Exceptions, and Program-Modifying Capability. Formal Methods in Systems Design, 20(2):187–222, 2002.
M. Srivas and M. Bickford. Formal Verification of a Pipelined Microprocessor. IEEE Software, 7(5):52–64, September 1990.
Author information
Authors and Affiliations
Corresponding author
Rights and permissions
Copyright information
© 2010 Springer Science+Business Media, LLC
About this chapter
Cite this chapter
Ray, S. (2010). Pipelined Machines. In: Scalable Techniques for Formal Verification. Springer, Boston, MA. https://doi.org/10.1007/978-1-4419-5998-0_9
Download citation
DOI: https://doi.org/10.1007/978-1-4419-5998-0_9
Published:
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4419-5997-3
Online ISBN: 978-1-4419-5998-0
eBook Packages: EngineeringEngineering (R0)