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Stimuli Generation for Functional Hardware Verification with Constraint Programming

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Hybrid Optimization

Part of the book series: Springer Optimization and Its Applications ((SOIA,volume 45))

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Abstract

We survey the application of constraint programming techniques for stimuli generation in functional hardware verification, which can be considered the largest and most important industrial application of constraint programming. We provide a thorough introduction to the application domain, aimed at people unfamiliar with this area. We show the sources of constraints and the unique aspects of the constraint satisfaction problems (CSPs) arising in this field. We then present CSP models of a wide variety of stimuli generation problems, as well as the state of the art techniques used to solve them. We also discuss the current challenges in this area, and the prospects of solving them by advancing constraint programming technology beyond the state of the art.

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Notes

  1. 1.

    Take, for example, the design of a processor. Then a test is simply a program, i.e., a sequence of assembly instructions, to be run on the processor. Only a very limited number of instruction sequences (including their parameters) form a valid program.

  2. 2.

    This statement is somewhat weakened in the case of BMC, as the proof is only for a specific set of assertions, and only within a limited number of cycles.

  3. 3.

    A pipeline is a micro-architecture mechanism that enables the concurrent computation of multiple instructions. The computation of a single instruction is broken into stages that are handled in corresponding stages of the pipeline. An instruction enters the pipeline and goes one by one through all the stages. Each stage can handle just one instruction at a time, but the pipeline can concurrently handle instructions at various stages.

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Acknowledgments

We are grateful to Amir Nahir, Gil Shurek, and Avi Ziv with whom we held extensive discussions. The material and book [12] for the Verification Course given by them at the Technion, Israel Institute of Technology, formed the basis for many of the ideas presented in Sect. 2. We also thank Eitan Marcus for his contribution to the sections related to checking and to Merav Aharoni, Sigal Asaf, and Yoav Katz for some of the figures in this chapter. The advancements in CP for verification presented here could not have been accomplished without the innovation, talent, and dedication of dozens of researchers and engineers at IBM Research – Haifa, and without the continuous feedback of verification engineers across IBM. The work of all those people is described and cited in many places in this chapter.

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  1. IBM Research – Haifa, Haifa University Campus, Haifa, 31905, Israel

    Allon Adir & Yehuda Naveh

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  1. Allon Adir
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  2. Yehuda Naveh
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Correspondence to Allon Adir or Yehuda Naveh .

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  1. , Department of Computer Science, Brown University, Providence, 02912, Rhode Island, USA

    Pascal van Hentenryck

  2. , Department of Electronics, Computer Scie, Università di Bologna, Viale Risorgimento 2, Bologna, 40136, Italy

    Michela Milano

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Adir, A., Naveh, Y. (2011). Stimuli Generation for Functional Hardware Verification with Constraint Programming. In: van Hentenryck, P., Milano, M. (eds) Hybrid Optimization. Springer Optimization and Its Applications, vol 45. Springer, New York, NY. https://doi.org/10.1007/978-1-4419-1644-0_16

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