Countermeasures

Abstract

Although many embedded devices offer more resistance to bus probing attacks due to their compact size, susceptibility to power or electromagnetic analysis attacks must be analyzed. Most attacks on embedded systems involve attacks on the implementation of cryptographic methods as discussed in Chap. 8. The focus of this chapter is on techniques for resisting attacks which may occur even when secure implementations exist. Specifically resistance to side channel analysis will be discussed and analyzed with experimental results. The objective of a countermeasure is to make an attack much harder. Of course it would be ideal to have a countermeasure which prevents any attacks using the side channel. However, we do not have perfect models for the side channel to guarantee that no attack is possible. Nor can we guarantee the use of truly random values in our countermeasure. Thus the quality of a countermeasure typically can be measured by the average number of traces required in order to launch a successful attack on a specific platform.

From a chip point of view, recall that external memory accesses or external data transfers (those which cross the chip boundary) dissipate large amounts of power and hence exhibit well-defined side channels which in general are easy to detect. These are an important focus for side channel resistance. However, secondary to off-chip loads, stores, or data transfers are on-chip memory accesses. This power dissipation largely depends on the size of memory, however, given large on-chip caches standard in most processor-based platforms it is an important secondary focus for security. Less significant but perhaps important for attacks where the chip is decapsulated are switching of on-chip busses if the busses have high enough capacitances and possibly but to a lesser extend datapaths and registers. Thus side channel analysis is expected to be successful if critical data is transferred “unprotected” on or off the chip as well as possibly on-chip memory access. Hence in many secure systems, it is important to consider resistance to side channels for critical data transfer to and from the chip, as well as critical data involved in memory accesses on and off of the chip.