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Reliable Testable Secure Systems

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Security in Embedded Devices

Part of the book series: Embedded Systems ((EMSY))

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Abstract

Although reliability has been extensively studied for decades in the space industry, it is now becoming evident that even ground-based embedded systems are facing similar reliability issues. This chapter will briefly discuss the single-event-upset (SEU) phenomena, also known as soft errors, and provide several examples of how reliability can be designed into secure embedded systems. The chapter will also discuss testability issues that relate to security and present some recent research in this area.

Reliable security is an extremely important area of engineering. Failure of a security application may have significant consequences, such as significant financial losses, personal injury in automobiles, losing control of a nuclear station, etc. Not only do security functions require rigorous testing before being put into the field but they also should be as reliable as possible. There is no room for errors in security. For example, a single error in AES causing one bit flip causes over 50% of the ciphertext bits to be in error. This is a result of the diffusion property of ciphers, which increases the effect of one bit over many bits in the output.

Ross Anderson reported the interesting case of a credit card, which was read by a misaligned card reader (Anderson 2001). The card reader should have detected errors in both the cryptographic computation (to detect forgery) as well as the simpler exclusive-or checksum computation (to detect errors). Instead and most unfortunate for the card owner, the cryptographic checksum successfully detected errors but the simpler checksum did not. This indicated incorrectly that the card was a forged card and the owner was “…arrested…and beaten up by the police.” ( Anderson 2001). The error apparently had been masked in the checksum causing much pain for the owner. This is likely not the first example of the disastrous impact of unreliablesecurity. Clearly designing for security includes designing for reactions to errors as well as resistance to attacks.

The problems of single-event-induced errors in integrated circuits riveted the attention of the commercial IC industry in the late 1970s, when it was recognized that the random, correctable errors in DRAMs within ground-based computers were due to single α-particles (May and Woods 1978)

Ma and Dressendorfer (1989)

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Authors and Affiliations

  1. Department of Electrical & Computer Engineering, University of Waterloo, 200 University Avenue W., Waterloo, ON, N2L 3G1, Canada

    Catherine H. Gebotys

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  1. Catherine H. Gebotys
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Correspondence to Catherine H. Gebotys .

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Gebotys, C.H. (2010). Reliable Testable Secure Systems. In: Security in Embedded Devices. Embedded Systems. Springer, Boston, MA. https://doi.org/10.1007/978-1-4419-1530-6_10

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  • DOI: https://doi.org/10.1007/978-1-4419-1530-6_10

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