Abstract
In this chapter, we explore the implementation of fault simulation on a graphics processing unit (GPU). In particular, we implement a parallel fault simulator. Fault simulation is inherently parallelizable, and the large number of threads that can be computed in parallel on a GPU results in a natural fit for the problemof parallel fault simulation.
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References
Commercial fault simulation tool. Licensing agreement with the tool vendor requires that we do not disclose the name of the tool or its vendor.
IWLS 2005 Benchmarks. http://www.iwls.org/iwls2005/benchmarks.html
NVIDIA Tesla GPU Computing Processor. http://www.nvidia.com/object/IO_43499.html
Abramovici, A., Levendel, Y., Menon, P.: A logic simulation engine. In: IEEE Transactions on Computer-Aided Design, vol. 2, pp. 82–94 (1983)
Agrawal, P., Dally, W.J., Fischer, W.C., Jagadish, H.V., Krishnakumar, A.S., Tutundjian, R.: MARS: A multiprocessor-based programmable accelerator. IEEE Design and Test 4 (5), 28–36 (1987)
Amin, M.B., Vinnakota, B.: Workload distribution in fault simulation. Journal of Electronic Testing 10(3), 277–282 (1997)
Amin, M.B., Vinnakota, B.: Data parallel fault simulation. IEEE Transactions on Very Large Scale Integration (VLSI) systems 7(2), 183–190 (1999)
Banerjee, P.: Parallel Algorithms for VLSI Computer-aided Design. Prentice Hall Englewood Cliffs, NJ (1994)
Beece, D.K., Deibert, G., Papp, G., Villante, F.: The IBM engineering verification engine. In: DAC ’88: Proceedings of the 25th ACM/IEEE Conference on Design Automation, pp. 218–224. IEEE Computer Society Press, Los Alamitos, CA (1988)
Gulati, K., Khatri, S.P.: Towards acceleration of fault simulation using graphics processing units. In: Proceedings, IEEE/ACM Design Automation Conference (DAC), pp. 822–827 (2008)
Ishiura, N., Ito, M., Yajima, S.: High-speed fault simulation using a vector processor. In: Proceedings of the International Conference on Computer-Aided Design (ICCAD) (1987)
Mueller-Thuns, R., Saab, D., Damiano, R., Abraham, J.: VLSI logic and fault simulation on general-purpose parallel computers. In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 12, pp. 446–460 (1993)
Narayanan, V., Pitchumani, V.: Fault simulation on massively parallel simd machines: Algorithms, implementations and results. Journal of Electronic Testing 3(1), 79–92 (1992)
Ozguner, F., Aykanat, C., Khalid, O.: Logic fault simulation on a vector hypercube multiprocessor. In: Proceedings of the third conference on Hypercube concurrent computers and applications, pp. 1108–1116 (1988)
Ozguner, F., Daoud, R.: Vectorized fault simulation on the Cray X-MP supercomputer. In: Computer-Aided Design, 1988. ICCAD-88. Digest of Technical Papers, IEEE International Conference on, pp. 198–201 (1988)
Parkes, S., Banerjee, P., Patel, J.: A parallel algorithm for fault simulation based on PROOFS. pp. 616–621. URL citeseer.ist.psu.edu/article/parkes95parallel.html
Patil, S., Banerjee, P.: Performance trade-offs in a parallel test generation/fault simulation environment. In: IEEE Transactions on Computer-Aided Design, pp. 1542–1558 (1991)
Pfister, G.F.: The Yorktown simulation engine: Introduction. In: DAC ’82: Proceedings of the 19th Conference on Design Automation, pp. 51–54. IEEE Press, Piscataway, NJ (1982)
Raghavan, R., Hayes, J., Martin, W.: Logic simulation on vector processors. In: Computer-Aided Design, Digest of Technical Papers, IEEE International Conference on, pp. 268–271 (1988)
Tai, S., Bhattacharya, D.: Pipelined fault simulation on parallel machines using the circuitflow graph. In: Computer Design: VLSI in Computers and Processors, pp. 564–567 (1993)
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Gulati, K., Khatri, S.P. (2010). Accelerating Fault Simulation Using Graphics Processors. In: Hardware Acceleration of EDA Algorithms. Springer, Boston, MA. https://doi.org/10.1007/978-1-4419-0944-2_8
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DOI: https://doi.org/10.1007/978-1-4419-0944-2_8
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