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Accelerating Boolean Satisfiability on a Graphics Processing Unit

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Hardware Acceleration of EDA Algorithms

Abstract

In this chapter we present a Boolean satisfiability solver with a new GPU-enhanced variable ordering heuristic. Our approach is implemented in a CPU-based procedure and leverages the parallelism of a graphics processing unit (GPU). The CPU implements a complete procedure (MiniSAT), while the GPU implements an approximate procedure (an implementation of survey propagation – SurveySAT).

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Correspondence to Kanupriya Gulati .

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Gulati, K., Khatri, S.P. (2010). Accelerating Boolean Satisfiability on a Graphics Processing Unit. In: Hardware Acceleration of EDA Algorithms. Springer, Boston, MA. https://doi.org/10.1007/978-1-4419-0944-2_6

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  • DOI: https://doi.org/10.1007/978-1-4419-0944-2_6

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