Abstract
In this chapter, we propose an FPGA-based SAT approach in which the traversal of the implication graph as well as conflict clause generation is performed in hardware, in parallel. In our approach, clause literals are stored in the FPGA slices. In order to solve large SAT instances, we heuristically partition the clauses into a number of ‘bins,’ each of which can fit in the FPGA. This is done in a preprocessing step.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
http://www.cs.chalmers.se/cs/research/formalmethods/minisat/main.html. The MiniSAT Page
Abramovici, M., de Sousa, J., Saab, D.: A massively-parallel easily-scalable satisfiability solver using reconfigurable hardware. In: Proceedings, Design Automation Conference (DAC), pp. 684–690 (1999)
Cook, S.: The complexity of theorem-proving procedures. In: Proceedings, Third ACM Symposium Theory of Computing, pp. 151–158 (1971)
Gulati, K., Paul, S., Khatri, S.P., Patil, S., Jas, A.: FPGA-based hardware acceleration for Boolean satisfiability. ACM Transaction on Design Automation of Electronic Systems 14(2), 1–11 (2009)
Mencer, O., Platzner, M.: Dynamic circuit generation for Boolean satisfiability in an object-oriented design environment. In: HICSS ’99: Proceedings of the Thirty-second Annual Hawaii International Conference on System Sciences-Volume 3, p. 3044. IEEE Computer Society, Washington, DC (1999)
Pagarani, T., Kocan, F., Saab, D., Abraham, J.: Parallel and scalable architecture for solving satisfiability on reconfigurable FPGA. In: Proceedings, IEEE Custom Integrated Circuits Conference (CICC), pp. 147–150 (2000)
Platzner, M., Micheli, G.D.: Acceleration of satisfiability algorithms by reconfigurable hardware. In: FPL ’98: Proceedings of the 8th International Workshop on Field-Programmable Logic and Applications, from FPGAs to Computing Paradigm, pp. 69–78. Springer-Verlag, London (1998)
Redekopp, M., Dandalis, A.: A parallel pipelined SAT solver for FPGAs. In: FPL ’00: Proceedings of The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications, pp. 462–468. Springer-Verlag, London (2000)
Safar, M., El-Kharashi, M., Salem, A.: FPGA-based SAT solver. In: Proceedings, Canadian Conference on Electrical and Computer Engineering, pp. 1901–1904 (2006)
Safar, M., Shalan, M., El-Kharashi, M.W., Salem, A.: Interactive presentation: A shift register based clause evaluator for reconfigurable SAT solver. In: DATE ’07: Proceedings of the Conference on Design, Automation and Test in Europe, pp. 153–158 (2007)
Silva, M., Sakallah, J.: GRASP – a new search algorithm for satisfiability. In: Proceedings of the International Conference on Computer-Aided Design (ICCAD), pp. 220–7 (1996)
Skliarova, I., Ferrari, A.B.: A software/reconfigurable hardware SAT solver. IEEE Transactions on Very Large Scale Integration Systems 12(4), 408–419 (2004)
Suyama, T., Yokoo, M., Sawada, H., Nagoya, A.: Solving satisfiability problems using reconfigurable computing. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 9(1), 109–116 (2001)
Zhao, Y., Malik, S., Wang, A., Moskewicz, M., Madigan, C.: Matching architecture to application via configurable processors: A case study with Boolean satisfiability problem. In: Proceedings, International Conference on Computer Design (ICCD), pp. 447–452 (2001)
Zhong, P., Martonosi, M., Ashar, P.: FPGA-based SAT solver architecture with near-zero synthesis and layout overhead. IEE Proceedings – Computers and Digital Techniques 147(3), 135–141 (2000)
Zhong, P., Martonosi, M., Ashar, P., Malik, S.: Accelerating Boolean Satisfiability with configurable hardware. In: Proceedings, IEEE Symposium on FPGAs for Custom Computing Machines, pp. 186–195 (1998)
Author information
Authors and Affiliations
Corresponding author
Rights and permissions
Copyright information
© 2010 Springer Science+Business Media, LLC
About this chapter
Cite this chapter
Gulati, K., Khatri, S.P. (2010). Accelerating Boolean Satisfiability on an FPGA. In: Hardware Acceleration of EDA Algorithms. Springer, Boston, MA. https://doi.org/10.1007/978-1-4419-0944-2_5
Download citation
DOI: https://doi.org/10.1007/978-1-4419-0944-2_5
Published:
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4419-0943-5
Online ISBN: 978-1-4419-0944-2
eBook Packages: EngineeringEngineering (R0)