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Accelerating Boolean Satisfiability on a Custom IC

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Hardware Acceleration of EDA Algorithms

Abstract

Boolean satisfiability (SAT) is a core NP-complete problem. Several heuristic software and hardware approaches have been proposed to solve this problem. In this work, we present a hardware solution to the SAT problem.We propose a custom IC to implement our approach, in which the traversal of the implication graph as well as conflict clause generation is performed in hardware, in parallel.

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Authors and Affiliations

  1. 109 Branchwood Trl, Coppell, TX, 75019, USA

    Kanupriya Gulati

  2. Department of Electrical & Computer Engineering, Texas A & M University, 214 Zachry Engineering Center, College Station, TX, 77843-3128, USA

    Sunil P. Khatri

Authors
  1. Kanupriya Gulati
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  2. Sunil P. Khatri
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Correspondence to Kanupriya Gulati .

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Gulati, K., Khatri, S.P. (2010). Accelerating Boolean Satisfiability on a Custom IC. In: Hardware Acceleration of EDA Algorithms. Springer, Boston, MA. https://doi.org/10.1007/978-1-4419-0944-2_4

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  • DOI: https://doi.org/10.1007/978-1-4419-0944-2_4

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  • Online ISBN: 978-1-4419-0944-2

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