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Hardware Platforms

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Hardware Acceleration of EDA Algorithms

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Abstract

As discussed in Chapter 1, single-threaded software applications no longer obtain significant gains in performance with the current processor scaling trends. With the growing complexity of VLSI designs, this is a significant problem for the electronic design automation (EDA) community. In addition to multi-core processors, hardware-based accelerators such as custom-designed ICs, reconfigurable hardware such as FPGAs, and streaming processors such as graphics processing units (GPUs) are being investigated as a potential solution to this problem. These platforms allow the CPU to offload compute-intensive portions of an application to the hardware for a faster computation, and the results are transferred back to the CPU upon completion. Different platforms are best suited for different application scenarios and algorithms. The pros and cons of the platforms under consideration are discussed in this chapter.

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Authors and Affiliations

  1. 109 Branchwood Trl, Coppell, TX, 75019, USA

    Kanupriya Gulati

  2. Department of Electrical & Computer Engineering, Texas A & M University, 214 Zachry Engineering Center, College Station, TX, 77843-3128, USA

    Sunil P. Khatri

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  1. Kanupriya Gulati
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  2. Sunil P. Khatri
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Correspondence to Kanupriya Gulati .

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Gulati, K., Khatri, S.P. (2010). Hardware Platforms. In: Hardware Acceleration of EDA Algorithms. Springer, Boston, MA. https://doi.org/10.1007/978-1-4419-0944-2_2

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  • DOI: https://doi.org/10.1007/978-1-4419-0944-2_2

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  • Print ISBN: 978-1-4419-0943-5

  • Online ISBN: 978-1-4419-0944-2

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