Skip to main content
SpringerLink
Log in

Power-Aware Test Data Compression and BIST

  • Chapter
  • First Online:
Power-Aware Testing and Test Strategies for Low Power Devices

Abstract

The test data volume for manufacturing test of modern devices is increasing rapidly. This is due to the facts that the transistor count for these chips is increasing exponentially and the use of advanced technology introduces new physical and timing-related defects, which require new types of test. It is well known that power consumption during test is much higher than in the functional mode due to increased switching activity in test mode. Therefore, efficient techniques that minimize both test data volume and test power consumption are required. Techniques such as test data compression and built-in-self-test (BIST) are used commonly to handle the problem of increased test data volume. In this chapter, several low-power state-of-the-art test data compression and BIST techniques are discussed. Their advantages and disadvantages are discussed from area, performance, and power point of view.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Log in via an institution
eBook
USD 16.99
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 119.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD 169.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

References

  • V. D. Agrawal, C. R. Kime and K. K. Saluja, “A tutorial on Built-In Self-Test, Part 1: Principles,” IEEE Design and Test of Computers, vol. 10, no. 1, pp. 73–82, 1993a.

    Article  Google Scholar 

  • V. D. Agrawal, C. R. Kime and K. K. Saluja, “A tutorial on Built-In Self-Test, Part 2: Applications,” IEEE Design and Test of Computers, vol. 10, no. 2, pp. 69–77, 1993b.

    Article  Google Scholar 

  • A. Al-Yamani, E. Chmeler, and M. Grinchuck, “Segmented addressable scan architecture,” Prof. IEEE VLSI Test Symposium, pp. 405–411, May 2005.

    Google Scholar 

  • N. Badereddine, Z. Wang, P. Girard, K. Chakrabarty, A. Virazel, S. Pravossoudovitch, and C. Landrault, “A selective scan slice encoding technique for test data volume and test power reduction,” Journal of Electronic Testing: Theory and Applications, vol. 24, pp. 353–364, August 2008.

    Article  Google Scholar 

  • D.H. Baik and K.K. Saluja, “Progressive random access scan: A simultaneous solution to test power, test data volume and test time,” Proc. IEEE International Test Conference, pp. 1–10, November 2005.

    Google Scholar 

  • P. H. Bardell, W. H. McAnney, and J. Savir, “Built-In Test for VLSI: Pseudorandom techniques,” John Wiley & Sons, New York, 1987.

    Google Scholar 

  • M. Bellos, D. Bakalis and D. Nikolos, “Scan cell ordering for low power BIST,” in Proc. International Symposium on VLSI Emerging Trends in VLSI Systems Design, 2004.

    Google Scholar 

  • B. Benware, C. Schurmyer, N. Tamarapalli, K. –H Tsai, S. Ranganathan, R. Madge, and P. Krishnamurthy, “Impact of multiple-detect test patterns on product quality,” in Proc. International Test Conference, October 2003, pp. 1031–1040.

    Google Scholar 

  • M. L. Bushnell and V. D. Agrawal, “Essentials of electronic testing,” Norwell, MA, Kluwer, 2000.

    Google Scholar 

  • K. J. Balakrishman and A. Touba, “Relationship between entropy and test data compression,” IEEE Transactions on VLSI Systems, pp. 386–395, 2007.

    Google Scholar 

  • D. Czysz, G. Mrugalski, J. Rajski, and J. Tyszer, “Low-power test data application in EDT environment through decompressor freeze,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 27, pp. 1278–1290, July 2008a.

    Article  Google Scholar 

  • D. Czysz, M. Kassab, X. Lin, G. Mrugalski, J. Rajski and J. Tyszer, “Low power scan shift and capture in the EDT environment,” in Proc. IEEE International Test Conference, October 2008b.

    Google Scholar 

  • K. Chakrabarty, “Test scheduling for core-based systems using mixed-integer linear programming,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 19, pp. 1163–1174, October 2000.

    Article  Google Scholar 

  • A. Chandra and K. Chakrabarty, “Low-power scan testing and test data compression for system-on-a-chip,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 21, pp. 597–604, May 2002.

    Article  Google Scholar 

  • A. Chandra and K. Chakrabarty, “System-on-a-chip test data compression and decompression architectures based on Golomb codes,” IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems, vol. 20, pp. 355–368, March 2001.

    Article  Google Scholar 

  • A. Chandra and K. Chakrabarty, “Test data compression and test resource partitioning for system-on-a-chip using frequency-directed run-length (FDR) codes,” IEEE Transactions on Computers, vol. 52, pp. 1076–1088, August 2003a.

    Article  Google Scholar 

  • A. Chandra and K. Chakrabarty, “A unified approach to reduce SOC test data volume, scan power and testing time,” IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems, vol. 22, pp. 352–362, March 2003b.

    Article  Google Scholar 

  • R. M. Chou, K. K. Saluja, and V. D. Agarwal, “Scheduling tests for VLSI systems under power constraints,” IEEE Transactions on VLSI Systems, vol. 5, pp. 175–185, June 1997.

    Article  Google Scholar 

  • R. M. Chou, K. K. Saluja, and V. D. Agrawal, “Power Constraint Scheduling of Tests,” in Proc. International Conference on VLSI Design, January 1994, pp. 271–274.

    Google Scholar 

  • H. Cox and J. Rajski, “On necessary and nonconflicting assignments in algorithmic test pattern generation,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 13, no. 4, pp. 515–530, April 1994.

    Article  Google Scholar 

  • F. Corno, M. Rebaudengo, and M. S. Reorda, “Low power BIST via nonlinear hybrid cellular automata,” in Proc. IEEE VLSI Test Symposium, pp. 29–34, April 2000.

    Google Scholar 

  • F. Corno, M. Rebaudengo, M. S. Reorda, and M. Violante, “A new BIST architecture for low power circuits,” in Proc. European Test Workshop, pp. 160–164, May 1999a.

    Google Scholar 

  • F. Corno, M. Rebaudengo, M.S. Reorda, and M. Violante, “Optimal vector selection for low power BIST,” in Proc. International Symposium on Defect and Fault Tolerance in VLSI Systems, November 1999b, pp. 219–226.

    Google Scholar 

  • G. L. Craig and C. R. Kime, “Pseudo-exhaustive adjacency testing: A BIST approach for stuck-open faults,” in Proc. International Test Conference, October 1985, pp. 126–137.

    Google Scholar 

  • V. Dabholkar, S. Chakravarty, I. Pomeranz, and S. M. Reddy, “Techniques for minimizing power dissipation in scan and combinational circuits during test application,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 17, pp. 1325–1333, December 1998.

    Article  Google Scholar 

  • F.-F. Ferhani and E. J. McCluskey, “Classifying bad chips and ordering test sets,” in Proc. International Test Conference, pp. 1–10, October 2006.

    Google Scholar 

  • S. Gerstendorfer and H.-J Wunderlich, “Minimized power consumption for scan-based BIST,” in Proc. International Test Conference, September 1999, pp. 77–84.

    Google Scholar 

  • P. Girard, L. Guiller, C. Landrault, and S. Pravossoudovitch, “An adjacency-based test pattern generator for low power BIST design,” in Proc Asian Test Symposium, December 2000, pp. 459–464.

    Google Scholar 

  • P. Girard, L. Guiller, C. Landrault, S. Pravossoudovitch, and H. J. Wunderlich, “A modified clock scheme for a low power BIST test pattern generator,” in Proc. VLSI Test Symposium, April 2001, pp. 306–311.

    Google Scholar 

  • P. Girard, L. Guiller, C. Landrault, and S. Pravossoudovitch, “A test vector inhibiting technique for low energy BIST design,” in Proc. VLSI Test Symposium, April 1999, pp. 407–412.

    Google Scholar 

  • S. K. Goel, N. Devta-Prasanna, and R. Turakhia, “Effective and efficient test pattern generation for small delay defects,” in Proc. VLSI Test Symposium, May 2009.

    Google Scholar 

  • P. T. Gonciari, B. M. Al-Hashimi and N. Nicolici, “Test data compression: The system integrator’s perspective,” in Proc. IEEE/ACM Design, Automation and Test in Europe (DATE) Conference, March 2003, pp. 726–731.

    Google Scholar 

  • B. Keller, M. Tegethoff, T. Bartenstein, and V. Chickermane, “An economic analysis and ROI model for nanometer test,” in Proc. International Test Conference, October 2004, pp. 518–524.

    Google Scholar 

  • I. Hamzaoglu and J. H. Patel, “Reducing test application time for full scan embedded cores,” Proc. IEEE International Symposium on Fault-Tolerant Computing, June 1999, pp. 260–267.

    Google Scholar 

  • J. Hartmann and G. Kenmnitz, “How to do weighted random testing for BIST,” in Proc. International Conference on Computer-Aided Design, 1993.

    Google Scholar 

  • S. Hellebrand, S. Tarnick, J. Rajski, and B. Courtois, “Generation of vector patterns through reseeding of multiple-polynomial linear feedback shift registers,” in Proc. International Test Conference, October 1992, pp. 120–129.

    Google Scholar 

  • Semiconductor Industry Association, International Technology Roadmap for Semiconductors (ITRS), 2007. [Online]. Available: http://www.itrs.net/Links/2007ITRS/Home2007.htm.

  • G. Karypis and V. Kumar, “A fast and high quality multilevel scheme for partitioning irregular graphs,” Technical Report 95–035, Department of Computer Science, University of Minnesota, 1988.

    Google Scholar 

  • B. Kruseman, A. K. Majhi, G. Gronthoud, and E. Eichenberger, “On hazard-free patterns for fine-delay testing,” in Proc. International Test Symposium, October 2004, pp. 213–222.

    Google Scholar 

  • J. Kuban and W. Bruce, “Self testing the Motorola MC6804P2,” IEEE Design and Test of Computers, vol. 1, no. 2, 1984.

    Google Scholar 

  • J. Lee and N. A. Touba, “LFSR-reseeding scheme achieving low-power dissipation during test,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 26, pp. 396–401, February 2007.

    Article  Google Scholar 

  • J. Li, X. Liu, Y. Zhang, Y. Hu, X. Li, and Q. Xu, “On capture power-aware test data compression for scan-based testing,” in Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD), May 2008, pp. 67–72.

    Google Scholar 

  • X. Liu and Q. Xu, “A generic framework for scan capture power reduction in fixed-length symbol-based test compression environment,” in Proc. IEEE/ACM Design, Automation and Test in Europe (DATE) Conference, April 2009.

    Google Scholar 

  • N. C. Lai, S. J. Wang, and Y. H. Fu, “Low power BIST with smoother and scanchain reorder,” in Proc. Asian Test Symposium, November 2004, pp. 40–45.

    Google Scholar 

  • J. Lee and N. A. Touba, “Low power BIST based on scan partitioning,” in Proc. International Symposium on Defect and Fault Tolerance in VLSI Systems, October 2005, pp. 33–41.

    Google Scholar 

  • X. Lin, K. H Tsai, C. Wang, M. Kassab, J. Rajski, T. Kobayashi, R. Klingenberg, Y. Sato, S. Hamada, and T. Aikyo, “Timing-aware ATPG for high quality at-speed testing of small delay defects,” in Proc. Asian Test Symposium, November 2006, pp. 139–146.

    Google Scholar 

  • S. Manich, A. Gabarro, M. Lopez, J. Figueras, P. Girard, L. Guiller, C. Landrault, S. Pravossoudovitch, P. Texieira, and M. Santos, “Low power BIST by filtering non-detecting vectors,” Journal of Electronic Testing: Theory and Applications, vol. 16, issue 3, 2000.

    Google Scholar 

  • G. Mrugalski J. Rajski, D. Czysz and J. Tyszer, “New test data decompressor for low power applications,” in Proc. IEEE/ACM Design Automation Conference, June 2007, pp. 539–544.

    Google Scholar 

  • N. Nicolici and B. M. Al-Hashimi, “Scan latch partitioning into multiple scan chains for power minimization in full scan sequential circuits,” in Proc. IEEE/ACM Design Automation and Test in Europe (DATE) Conference, March 2000, pp. 715–722.

    Google Scholar 

  • M. Nourani and M. H. Tehranipoor, “RL-Huffman encoding for test compression and power reduction in scan applications,” ACM Transactions on Design Automation of Electronic Systems, vol. 10, pp. 91–115, January 2005.

    Article  Google Scholar 

  • I. Pomeranz, S. M. Reddy, and R. Guo, “Static test compaction for synchronous sequential circuits based on vector restoration,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp. 1040–1049, July 1999.

    Google Scholar 

  • I. Pomeranz and S. M. Reddy, “3-weight pseudo-random test generation based on a deterministic test set for combinational and sequential circuits,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 12, pp. 1050–1058, 1993.

    Article  Google Scholar 

  • P. M. Rosinger, P. T. Gonciari, B. M. Al-Hashimi, and N. Nicolici, “Simultaneous reduction in volume of test data and power dissipation for systems-on-chip,” Electronic Letters, vol. 37, no. 24, pp. 1434–1436, November 2001.

    Article  Google Scholar 

  • P. M. Rosinger, P. T. Gonciari, B. M. Al-Hashimi, and N. Nicolici, “Analysing trade-offs in scan power and test data compression for systems-on-a-chip,” IEE Proc.-Computers and Digital Techniques, vol. 149, no. 4, pp. 188–196, July 2002a.

    Article  Google Scholar 

  • P. M. Rosinger, B. M. Al-Hashimi, and N. Nicolici, “Low power mixed mode BIST based on mask pattern generation using dual LFSR reseeding,” in Proc. International Conference on Computer Design (ICCD), pp. 474–479, 2002b.

    Google Scholar 

  • P. Rosinger, B. M. Al-Hashimi, and N. Nicolici, “Scan architecture with mutually exclusive scan segment activation for shift- and capture-power reduction,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 23, pp. 1142–1153, 2004.

    Article  Google Scholar 

  • R. Sankaralingam, R. R. Oruganti, and N. A. Touba, “Static compaction techniques to control scan vector power dissipation,” in Proc. IEEE VLSI Test Symposium, April 2000, pp. 35–40.

    Google Scholar 

  • J. Saxena, K. Butler, and L. Whetsel, “An analysis of power reduction techniques in scan testing,” in Proc. International Test Conference, October 2001, pp. 670–677.

    Google Scholar 

  • M. Sugihara, H. Date, and H. Yasuura, “A novel test methodology for core-based system LSI’s and a testing time minimization problem,” in Proc. International Test Conference, October 1998, pp. 465–472.

    Google Scholar 

  • N. Tamarapalli and J. Rajski, “Constructive multi-phase test point insertion for scan-based BIST,” in Proc. International Test Conference, October 1996, pp. 649–658.

    Google Scholar 

  • N. Touba and E. J. McCluskey, “Altering a pseudo-random bit sequence for scan-based BIST,” in Proc. International Test Conference, October 1996, pp. 167–175.

    Google Scholar 

  • R. Turakhia, W. R. Daasch, M. Ward, and J. van Slyke, “Silicon evaluation of longest path avoidance testing for small delay defects,” in Proc. International Test Conference, pp. 1–10, October 2007.

    Google Scholar 

  • B. Vermeulen, C. Hora, B. Kruseman, E. J. Marinissen, and R. van Rijsinge, “Trends in testing integrated circuits,” in Proc. International Test Conference, October 2004, pp. 688–697.

    Google Scholar 

  • J. Waicukauski, E. Lindbloom, E. Eichelberger, and O. Forlenza, “A method for generating weighted random test patterns,” IEEE Transactions on Computers, vol. 33, no. 2, 1989.

    Google Scholar 

  • S. Wang and S. K. Gupta, “ATPG for heat dissipation minimization during scan testing,” in Proc. International Test Conference, October 1997a, pp. 250–258.

    Google Scholar 

  • S. Wang and S. K. Gupta, “DS-LFSR: A new BIST TPG for low heat dissipation,” in Proc. International Test Conference, November 1997b, pp. 848–857.

    Google Scholar 

  • S. Wang and S. K. Gupta, “LT-RTPG: A new test-per-scan BIST TPG for low switching activity,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 25, no. 8, August 2006.

    Google Scholar 

  • S. Wang and S. K. Gupta, “LT-RTPG: A new test-per-scan BIST TPG for low heat dissipation,” in Proc. International Test Conference, September 1999, pp. 85–94.

    Google Scholar 

  • S. Wang, “Minimizing heat dissipation during test application,” Ph.D. Dissertation, University of Southern California, 1998.

    Google Scholar 

  • S. Wang, “Low hardware overhead scan based 3-weight weighted random BIST,” in Proc. International Test Conference, October 2001, pp. 868–877.

    Google Scholar 

  • S. Wang, “Generation of low power dissipation and high fault coverage patterns for scan-based BIST,” in Proc. International Test Conference, October 2002, pp. 834–843.

    Google Scholar 

  • N. H. E Weste and K. Eshraghian, “Principles of CMOS VLSI design: A systems perspective.” 2nd Edition, Addison-Wesley, MA, 1992.

    Google Scholar 

  • Z. Wang and K. Chakrabarty, “Test data compression for IP embedded cores using selective encoding of scan slices,” in Proc. IEEE International Test Conference, November 2005.

    Google Scholar 

  • Z. Wang and K. Chakrabarty, “Test data compression using selective encoding of scan slices,” IEEE Transactions on VLSI Systems, vol. 16, pp. 1429–1440, November 2008.

    Article  Google Scholar 

  • L. Whetsel, “Adapting scan architectures for low power operation,” in Proc. International Test Conference, October 2000, pp. 863–872.

    Google Scholar 

  • L. Xu, Y. Sun, and H. Chen, “Scan array solution for testing power and testing time,” in Proc. International Test Conference, October 2001, pp. 652–659.

    Google Scholar 

  • M. Yilmaz, K. Chakrabarty, and M. Tehranipoor, “Test pattern grading and pattern selection for small delay defects,” in Proc. VLSI Test Symposium, April 2008, pp. 233–239.

    Google Scholar 

  • K. Yang, K.-T. Cheng, and L.-C. Wang, “TranGen: A SAT-based ATPG for path-oriented transition faults,” in Proc. Asia South Pacific Design Automation Conference, January 2004, pp. 92–97.

    Google Scholar 

  • X. Zhang and K. Roy, “Peak power reduction in low power BIST,” in Proc. IEEE International Symposium on Quality of Electronic Design, March 2000, pp. 425–432.

    Google Scholar 

  • Y. Zorian, “A distributed BIST control scheme for complex VLSI devices,” in Proc. VLSI Test Symposium, April 1993, pp. 4–9.

    Google Scholar 

Download references

Author information

Authors and Affiliations

  1. LSI Corporation, Milpitas, CA, USA

    Sandeep Kumar Goel

  2. Duke University, Dhuram, NC, USA

    Krishnendu Chakrabarty

Authors
  1. Sandeep Kumar Goel
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Krishnendu Chakrabarty
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Sandeep Kumar Goel .

Editor information

Editors and Affiliations

  1. de Robotique de Microélectronique de, LIRMM - Laboratoire d'Informatique, Rue Ada 161, Montpellier, 34392, France

    Patrick Girard

  2. Dept. Electrical &, McMaster University, Main Street West 1280, Hamilton, L8S 4K1, Canada

    Nicola Nicolici

  3. Dept. Computer Science & Electronics, Kyushu Institute of Technology, Kawazu 680-4, Iizuka, 820-8502, Japan

    Xiaoqing Wen

Rights and permissions

Reprints and permissions

Copyright information

© 2010 Springer Science+Business Media, LLC

About this chapter

Cite this chapter

Goel, S.K., Chakrabarty, K. (2010). Power-Aware Test Data Compression and BIST. In: Girard, P., Nicolici, N., Wen, X. (eds) Power-Aware Testing and Test Strategies for Low Power Devices. Springer, Boston, MA. https://doi.org/10.1007/978-1-4419-0928-2_5

Download citation

  • DOI: https://doi.org/10.1007/978-1-4419-0928-2_5

  • Published:

  • Publisher Name: Springer, Boston, MA

  • Print ISBN: 978-1-4419-0927-5

  • Online ISBN: 978-1-4419-0928-2

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics

Search

Navigation