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Fundamentals of VLSI Testing

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Power-Aware Testing and Test Strategies for Low Power Devices

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Abstract

Very-large-scale integration (VLSI) testing encompasses all spectrums of test methods and structures embedded in a system-on-chip (SOC) to ensure the quality of manufactured devices during manufacturing test. The test methods typically include fault simulation and test generation, so that quality test patterns can be supplied to each device. The test structures often employ specific design for testability (DFT) techniques, such as scan design and built-in self-test (BIST), to test the digital logic portions of the device. To provide readers with basic understanding of the most recent DFT advances in logic testing, memory testing, and SOC testing for low-power device applications, this chapter covers a number of fundamental test methods and DFT structures to facilitate testing of modern SOC circuits. These methods and structures are required to improve the product quality and reduce the defect level and test cost of the manufactured devices, while at the same time simplifying the test, debug, and diagnosis tasks.

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References

  • M. Abramovici, M. A. Breuer, and A. D. Friedman, Digital Systems Testing and Testable Design, IEEE Press, Piscataway, NJ, 1990.

    Google Scholar 

  • E. A. Amerasekera and D. S. Campbell, Failure Mechanisms in Semiconductor Devices, John Wiley & Sons, London, 1987.

    Google Scholar 

  • S. Bahukudumbi and K. Chakrabarty, “Wafer-Level Modular Testing of Core-Based SOCs,” IEEE Trans. on VLSI Systems, vol. 15, no. 10, pp. 1144–1154, Oct. 2007.

    Article  Google Scholar 

  • P. H. Bardell and W. H. McAnney, “Self-Testing of Multiple Logic Modules,” in Proc. of the International Test Conf., Nov. 1982, pp. 200–204.

    Google Scholar 

  • M. L. Bushnell and V. D. Agrawal, Essentials of Electronic Testing for Digital, Memory & Mixed-Signal VLSI Circuits, Springer, Boston, 2000.

    Google Scholar 

  • A. Chandra and K. Chakrabarty, “System-on-a-Chip Test-Data Compression and Decompression Architectures Based on Golomb Codes,” IEEE Trans. on Computer-Aided Design, vol. 20, no. 3, pp. 355–368, Mar. 2001.

    Article  Google Scholar 

  • M. Chao, K.-T. Cheng, S. Wang, S. Chakradhar, and W. Wei, “A Hybrid Scheme for Compacting Test Responses with Unknown Values,” in Proc. of the International Conf. on Computer-Aided Design, Nov. 2007, pp. 513–519.

    Google Scholar 

  • B. Cheung and L.-T. Wang, “The Seven Deadly Sins of Scan-Based Designs,” Integrated System Design, Aug. 1997. (http://www.eetimes.com/editorial/1997/test9708.html).

  • K.-T. Cheng and L.-C. Wang, “Chapter 22: Automatic Test Pattern Generation,” in EDA for IC System Design, Verification, and Testing, L. Scheffer, L. Lavagno, and G. Martin, editors, CRC Press, Boca Raton, FL, 2006.

    Google Scholar 

  • K. L. Cheng, J. R. Huang, C. W. Wang, C. Y. Lo, L. M. Denq, C. T. Huang, C. W. Wu, S. W. Hung, and J. Y. Lee, “An SOC Test Integration Platform and Its Industrial Realization,” in Proc. of the International Test Conf., Oct. 2004, pp. 1213–1222.

    Google Scholar 

  • E. B. Eichelberger and T. W. Williams, “A Logic Design Structure for LSI Testability,” Journal of Design Automation and Fault-Tolerant Computing, vol. 2, no. 2, pp. 165–178, Feb. 1978.

    Google Scholar 

  • J. M. Emmert, C. E. Stroud, and J. R. Bailey, “A New Bridging Fault Model for More Accurate Fault Behavior,” in Proc. of the Design Automation Conf., Sep. 2000, pp. 481–485.

    Google Scholar 

  • H. Fujiwara and S. Toida, “The Complexity of Fault Detection Problems for Combinational Logic Circuits,” IEEE Trans. on Computers, vol. 31, no. 6, pp. 555–560, Jun. 1982.

    Article  MATH  Google Scholar 

  • P. Girard, “Survey of Low-Power Testing of VLSI Circuits,” IEEE Design & Test of Computers, vol. 19, no. 3, pp. 82–92, May-Jun. 2002.

    Article  MathSciNet  Google Scholar 

  • D. Gizopoulos, editor, Advances in Electronic Testing: Challenges and Methodologies, Morgan Kaufmann, San Francisco, 2006.

    Google Scholar 

  • S. K. Goel, K. Chiu, E. J. Marinissen, T. Nguyen, and S. Oostdijk, “Test Infrastructure Design for the Nexperia Home Platform PNX8550 System Chip,” in Proc. of the Design, Automation, and Test in Europe Conf., Feb. 2004, pp. 108–113.

    Google Scholar 

  • L. H. Goldstein and E. L. Thigpen, “SCOAP: Sandia Controllability/Observability Analysis Program,” in Proc. of the Design Automation Conf., Jun. 1980, pp. 190–196.

    Google Scholar 

  • S. Hamdioui, Testing Static Random Access Memories, Springer, Boston, 2004.

    MATH  Google Scholar 

  • I. Hamzaoglu and J. H. Patel, “Reducing Test Application Time for Full Scan Embedded Cores,” in Proc. of the Fault-Tolerant Computing Symp., Jul. 1999, pp. 260–267.

    Google Scholar 

  • P. H. Ibarra and S. K. Sahni, “Polynomially Complete Fault Detection Problems,” IEEE Trans. on Computers, vol. C-24, no. 3, pp. 242–249, Mar. 1975.

    Article  MathSciNet  Google Scholar 

  • IEEE Std. 1149.1–2001, IEEE Standard Test Access Port and Boundary Scan Architecture, IEEE Press, New York, 2001.

    Google Scholar 

  • IEEE Std. 1450.6–2001, Core Test Language (CTL), IEEE Press, New York, 2001.

    Google Scholar 

  • IEEE Std. 1500–2005, IEEE Standard for Embedded Core Test, IEEE Press, New York, 2005.

    Google Scholar 

  • V. Iyengar, K. Chakrabarty, and E. J. Marinissen, “Test Wrapper and Test Access Mechanism Co-Optimization for System-on-a-Chip,” Journal of Electronic Testing: Theory and Applications, Special Issue on Low Power Testing, vol. 18, pp. 213–230, Apr. 2002.

    Google Scholar 

  • V. Iyengar, K. Chakrabarty, and E. J. Marinissen, “Test Access Mechanism Optimization, Test Scheduling and Tester Data Volume Reduction for System-on-Chip,” IEEE Trans. on Computers, vol. 52, no. 12, pp. 1619–1632, Dec. 2003.

    Article  Google Scholar 

  • S. K. Jain and V. D. Agrawal, “Statistical Fault Analysis,” IEEE Design & Test of Computers, vol. 2, no. 2, pp. 38–44, Feb. 1985.

    Article  Google Scholar 

  • A. Jas and N. A. Touba, “Test Vector Compression via Cyclical Scan Chains and Its Application to Testing Core-Based Designs,” in Proc. of the International Test Conf., Oct. 1998, pp. 458–464.

    Google Scholar 

  • A. Jas, J. Ghosh-Dastidar, M. Ng, and N. A. Touba, “An Efficient Test Vector Compression Scheme Using Selective Huffman Coding,” IEEE Trans. on Computer-Aided Design, vol. 22, no. 6, pp. 797–806, Jun. 2003.

    Article  Google Scholar 

  • N. K. Jha and S. K. Gupta, Testing of Digital Systems, Cambridge University Press, London, 2003.

    Google Scholar 

  • R. Kapur, S. Mitra, and T. W. Williams, “Historical Perspective on Scan Compression,” IEEE Design & Test of Computers, vol. 25 no. 2, pp. 114–120, Mar.-Apr. 2008.

    Article  Google Scholar 

  • B. Könemann, J. Mucha, and G. Zwiehoff, “Built-In Logic Block Observation Techniques,” in Proc. of the International Test Conf., Oct. 1979, pp. 37–41.

    Google Scholar 

  • B. Könemann, C. Barnhart, and B. Keller, “Real-Time Decoder for Scan Test Patterns,” United States Patent No. 6,611,933, Aug. 26, 2003.

    Google Scholar 

  • K.-J. Lee, J.-J. Chen, and C.-H. Huang, “Broadcasting Test Patterns to Multiple Circuits,” IEEE Trans. on Computer-Aided Design, vol. 18, no. 12, pp. 1793–1802, Dec. 1999.

    Article  Google Scholar 

  • K.-J. Lee, C.-Y. Chu, and Y.-T. Hong, “An Embedded Processor Based SOC Test Platform,” in Proc. of the International Symp. on Circuits and Systems, 3, May 2005, pp. 2983–2986.

    Google Scholar 

  • E. Marinissen, R. Kapur, M. Lousberg, T. McLaurin, M. Ricchetti, and Y. Zorian, “On IEEE P1500’s Standard for Embedded Core Test,” Journal of Electronic Testing: Theory and Applications, Special Issue on Low Power Testing, vol. 18, no. 4, pp. 365–383, Aug. 2002.

    Google Scholar 

  • T. C. May and M. H. Woods, “Alpha-Particle-Induced Soft Errors in Dynamic Memories,” IEEE Trans. on Electron Devices, vol. ED-26, no. 1, pp. 2–9, Jan. 1979.

    Article  Google Scholar 

  • E. J. McCluskey, Logic Design Principles: With Emphasis on Testable Semicustom Circuits, Prentice-Hall, Englewood Cliffs, NJ, 1986.

    Google Scholar 

  • E. J. McCluskey and F. Buelow, “IC Quality and Test Transparency,” in Proc. of the International Test Conf., Sep. 1988, pp. 295–301.

    Google Scholar 

  • S. Mitra and K. S. Kim, “X-Compact: An Efficient Response Compaction Technique,” IEEE Trans. on Computer-Aided Design, vol. 23, no. 3, pp. 421–432, Mar. 2004.

    Article  Google Scholar 

  • A. Ney, P. Girard, C. Landrault, S. Pravossoudovitch, A. Virazel, and M. Bastian, “Dynamic Two-Cell Incorrect Read Fault due to Resistive-Open Defects in the Sense Amplifiers of SRAMs”, in Proc. of European Test Symp., May 2007, pp. 97–104.

    Google Scholar 

  • M. Nahvi and A. Ivanov, “Indirect Test Architecture for SoC Testing,” IEEE Trans. on Computer-Aided Design, vol. 23, no. 7, pp. 1128–1142, Jul. 2004.

    Google Scholar 

  • M. Ohlsson, P. Dyreklev, K. Johansson, and P. Alfke, “Neutron Single Event Upsets in SRAM-Based FPGAs,” in Proc. of the Nuclear and Space Radiation Effects Conf., Jul. 1998, pp. 177–180.

    Google Scholar 

  • P. Pande, C. Crecu, A. Ivanov, R. Saleh, and G. de Micheli, “Design, Synthesis and Test of Networks on Chip: Challenges and Solutions,” IEEE Design & Test of Computers, vol. 22, no. 5, pp. 404–413, Sep.-Oct. 2005.

    Article  Google Scholar 

  • K. P. Parker and E. J. McCluskey, “Probability Treatment of General Combinational Networks,” IEEE Trans. on Computers, vol. 24, no. 6, pp. 668–670, Jun. 1975.

    Article  MATH  MathSciNet  Google Scholar 

  • J. Rajski, J. Tyszer, M. Kassab, and N. Mukherjee, “Embedded Deterministic Test,” IEEE Trans. on Computer-Aided Design, vol. 23, no. 5, pp. 776–792 May 2004.

    Article  Google Scholar 

  • S. M. Reddy, K. Miyase, S. Kajihara, and I. Pomeranz, “On Test Data Volume Reduction for Multiple Scan Chain Designs,” in Proc. of the VLSI Test Symp., Apr. 2002, pp. 103–108.

    Google Scholar 

  • J. P. Roth, “Diagnosis of Automata Failure: A Calculus & A Method,” IBM Journal of Research and Development, vol. 10, no. 4, pp. 278–291, Apr. 1966.

    Article  MATH  Google Scholar 

  • R. Saleh, S. Wilton, S. Mirabbasi, A. Hu, M. Greenstreet, G. Lemieux, P. Pande, C. Grecu, and A. Ivanov, “System on Chip: Reuse and Integration,” Proceedings of the IEEE, vol. 94, no. 6, pp. 1050–1069, Jun. 2006.

    Article  Google Scholar 

  • Y. Sato, S. Hamada, T. Maeda, A. Takatori, Y. Nozuyama, and S. Kajihara, “Invisible Delay Quality – SDQM Model Lights Up What Could Not Be Seen,” in Proc. of the International Test Conf., Nov. 2005, Paper 47.1.

    Google Scholar 

  • J. Savir, G. S. Ditlow, and P. H. Bardell, “Random Pattern Testability,” IEEE Trans. on Computer, vol. C-3, no. 1, pp. 79–90, Jan. 1984.

    Article  Google Scholar 

  • SIA, “The International Technology Roadmap for Semiconductors: 2007 Update,” Semiconductor Industry Association, San Jose, CA, http://public.itrs.net, 2007.

  • N. Sitchinava, S. Samaranayake, R. Kapur, E. Gizdarski, F. Neuveux, and T. W. Williams, “Changing the Scan Enable During Shift,” in Proc. of the VLSI Test Symp., Apr. 2004, pp. 73–78.

    Google Scholar 

  • C. E. Stroud, “An Automated Built-In Self-Test Approach for General Sequential Logic Synthesis,” in Proc. of the Design Automation Conf., Jun. 1988, pp. 3–8.

    Google Scholar 

  • C. E. Stroud, A Designer’s Guide to Built-In Self-Test, Springer, Boston, 2002.

    Google Scholar 

  • N. A. Touba, “Survey of Test Vector Compression Techniques,” IEEE Design & Test of Computers, vol. 23, no. 4, pp. 294–303, Jul.-Aug. 2006.

    Article  Google Scholar 

  • N. A. Touba, “X-Canceling MISR – An X-Tolerant Methodology for Compacting Output Responses with Unknowns Using a MISR,” in Proc. of the International Test Conf., Oct. 2007, Paper 6.2.

    Google Scholar 

  • H.-C. Tsai, K.-T. Cheng, and S. Bhawmik, “Improving the Test Quality for Scan-Based BIST Using a General Test Application Scheme,” in Proc. of the Design Automation Conf., Jun. 1999, pp. 748–753.

    Google Scholar 

  • A. van de Goor, Testing Semiconductor Memories: Theory and Practice, John Wiley & Sons, London, 1991.

    Google Scholar 

  • A. van de Goor, G. Gaydadjiev, V. Jarmolik, and V. Mikitjuk, “March LR: A Test for Realistic Linked Faults,” in Proc. of the VLSI Test Symp., Apr. 1996, pp. 272–280.

    Google Scholar 

  • R. Wadsack, “Fault Modeling and Logic Simulation for CMOS and NMOS Integrated Circuits,” The Bell System Technical Journal, vol. 57, no. 5, pp. 1449–1474, May 1978.

    Google Scholar 

  • L.-T. Wang and E. Law, “An Enhanced Daisy Testability Analyzer (DTA),” in Proc. of the Design Automation Conf., Oct. 1985, pp. 223–229.

    Google Scholar 

  • L.-T. Wang, X. Wen, H. Furukawa, F.-S. Hsu, S. H. Lin, S. W. Tsai, K. S. Abdel-Hafez, and S. Wu, “VirtualScan: A New Compressed Scan Technology for Test Cost Reduction,” in Proc. of the International Test Conf., Oct. 2004, pp. 916–925.

    Google Scholar 

  • L.-T. Wang, C.-W. Wu, and X. Wen, editors, VLSI Test Principles and Architectures: Design for Testability, Morgan Kaufmann, San Francisco, 2006.

    Google Scholar 

  • L.-T. Wang, C. E. Stroud, and N. A. Touba, editors, System-on-Chip Test Architectures: Nanometer Design for Testability, Morgan Kaufmann, San Francisco, 2007.

    Google Scholar 

  • L.-T. Wang, C. E. Stroud, and K.-T. Cheng, “Logic Testing,” in Wiley Encyclopedia of Computer Science and Engineering, B. W. Wah (ed.), John Wiley & Sons, Hoboken, NJ, 2008a.

    Google Scholar 

  • L.-T. Wang, X. Wen, S. Wu, Z. Wang, Z. Jiang, B. Sheu, and X. Gu, “VirtualScan: Test Compression Technology Using Combinational Logic and One-Pass ATPG,” IEEE Design & Test of Computers, vol. 25, no. 2, pp. 122–130, Mar.-Apr. 2008b.

    Article  Google Scholar 

  • L.-T. Wang, B. Sheu, Z. Jiang, Z. Wang, and S. Wu, “Method and Apparatus for Broadcasting Test Patterns in a Scan Based Integrated Circuit,” United States Patent No. 7,412,637, Aug. 12, 2008c.

    Google Scholar 

  • L.-T. Wang, R. Apte, S. Wu, B. Sheu, K.-J. Lee, X. Wen, W.-B. Jone, J. Guo, W.-S. Wang, H.-J. Chao, J. Liu, Y. Niu, Y.-C. Sung, C.-C. Wang, and F. Li, “Turbo1500: Core-Based Design for Test and Diagnosis,” IEEE Design & Test of Computers, vol. 26, no. 1, pp. 26–35, Jan.-Feb. 2009.

    Article  Google Scholar 

  • X. Wen, S. Kajihara, K. Miyase, T. Suzuki, K. K. Saluja, L.-T. Wang, K. S. Abdel-Hafez, and K. Kinoshita, “A New ATPG Method for Efficient Capture Power Reduction During Scan Testing,” in Proc. of the VLSI Test Symp., May 2006, pp. 58–63.

    Google Scholar 

  • T. W. Williams and N. C. Brown, “Defect Level as a Function of Fault Coverage,” IEEE Trans. on Computers, vol. 30, no. 12, pp. 987–988, Dec. 1981.

    Article  Google Scholar 

  • T. W. Williams and K. Parker, “Design for Testability – A Survey,” Proceedings of the IEEE, vol. 71, no. 1, pp. 98–112, Jan. 1983.

    Article  Google Scholar 

  • P. Wohl, J. A. Waicukauski, and S. Ramnath, “Fully X-Tolerant Combinational Scan Compression,” in Proc. of the International Test Conf., Oct. 2007, Paper 6.1.

    Google Scholar 

  • Q. Xu and N. Nicolici, “Resource-Constrained System-on-a-Chip Test: A Survey,” IEE Proceedings – Computers and Digital Techniques, vol. 152, no. 1, pp. 67–81, Jan. 2005.

    Article  Google Scholar 

  • Y. Zorian and A. Yessayan, “IEEE 1500 Utilization in SOC Test and Design,” in Proc. of the International Test Conf., Nov. 2005, pp. 1203–1212.

    Google Scholar 

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Acknowledgements

The authors would like to thank Professor Xiaoqing Wen of Kyushu Institute of Technology for providing a portion of the material in the Scan Design section, Professor Kwang-Ting (Tim) Cheng of the University of California at San Barbara for providing a portion of the material in the Logic Testing section, and Professor Kuen-Jong Lee of National Cheng Kung University for providing a portion of the material in the System-on-Chip Testing section. The authors also would like to thank Professor Wen-Ben Jone of University of Cincinnati, Professor Nur A. Touba of the University of Texas at Austin, Professor Michael S. Hsiao of Virginia Tech, and the three coeditors of this book for reviewing the chapter and providing very helpful comments. The authors drew material from their prior work in the Logic Testing article in WileyEncyclopedia of Computer Science and Engineering (2008) published by John Wiley & Sons. Material was also drawn from the three DFT and EDA textbooks published by Morgan Kaufmann: VLSI Test Principles and Architectures: Design for Testability (2006), System-on-Chip Test Architectures: Nanometer Design for Testability (2007), and Electronic Design Automation: Synthesis, Verification, and Test (2009).

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  1. SynTest Technologies Inc., Sunnyvale, CA, USA

    Laung-Terng Wang

  2. Auburn University, Auburn, AL, USA

    Charles E. Stroud

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  1. Laung-Terng Wang
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  1. de Robotique de Microélectronique de, LIRMM - Laboratoire d'Informatique, Rue Ada 161, Montpellier, 34392, France

    Patrick Girard

  2. Dept. Electrical &, McMaster University, Main Street West 1280, Hamilton, L8S 4K1, Canada

    Nicola Nicolici

  3. Dept. Computer Science & Electronics, Kyushu Institute of Technology, Kawazu 680-4, Iizuka, 820-8502, Japan

    Xiaoqing Wen

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Wang, LT., Stroud, C.E. (2010). Fundamentals of VLSI Testing. In: Girard, P., Nicolici, N., Wen, X. (eds) Power-Aware Testing and Test Strategies for Low Power Devices. Springer, Boston, MA. https://doi.org/10.1007/978-1-4419-0928-2_1

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