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The Copper Damascene Process and Chemical Mechanical Polishing

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Copper Interconnect Technology

The American Heritage Illustrated Encyclopedic Dictionary defines damascene as a native inhabitant of Damascus (Damaskus), which is a major city in the north-west of Syria. The word Damask means patterned silk fabrics woven in Damascus, a city notable for manufacturing and shipment of damascened steel sword blades, which were exceptionally hard and resilient. In French, damascene is damas quiner means to decorate in the manner of Damascus blades or steel from Damasquine of Damascus. Thus the word damascene can be taken literally as the process of decorating a metal with wavy patterns of gold or silver. However, in integrated circuits (ICs) the damascene process means an elegant technique of inlaying metal (copper) for interconnect which avoids the complicated process of metal etching.

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References

  1. A. West, Theory of filling of high aspect ratio trenches and vias in presence of additives, J. Electrochem. Soc., 147, 227 (2000) and J. Van Olmen et al., AMC Tech Dig., 5 (2007)

    Google Scholar 

  2. P.C. Andricacos, C. Uzoh, J.O. Dukovic, J. Horkans, and H. Deligiani, IBM, J. Res. Dev., 42, 567 (1998)

    Article  Google Scholar 

  3. E.K. Broadbent et al., Experimental and analytical study of seed layer resistance for copper damascene electroplating, J. Vac. Sci. Technol., B-17, 2584 (1999)

    Google Scholar 

  4. S. Wolf, Silicon processing for VLSI Era, Lattice Press, Sunset Beach, CA, Vol. 4, Chapt-15 (1986) and also R.L. Opila and D.W. Hess, A century of dielectric science and technology, J. Electrochem. Soc., 150 (1), S1–S10 (2003)

    Google Scholar 

  5. T.K. Gupta, Hand book of thick and thin film hybrid microelectronics, Wiley, NJ, Chapter 4 (2003)

  6. S. Wolf, Deep Sub-micron process technology, in Silicon processing for VLSI era, Lattice Press, Sunset beach, CA, Vol. 4 (2002) and also R.J. Guttman et al., Integration of copper multilevel interconnects with oxide and polymer interlevel dielectrics, Thin Solid Films, 270, 472 (1995)

    Google Scholar 

  7. J.C. Maisonobe, G. Passemard, C. Lacour, T. Motte, T. Noel, and J. Torres, Silk compatibility with IMD process using copper metallization, Microelectron. Eng., 50, 25 (2000) and J. Van Olmen et al., IEEE IITC, Tech Dig., 49 (2007)

    Google Scholar 

  8. Y. Gotkis and S. Guha, Cu-CMP for dual damascene technology, J. Electronic Mater., 30 (4) (2001)

    Google Scholar 

  9. T.N. Theis, The Future of interconnection technology, IBM J. Res. Dev., 44 (3) (2000)

    Google Scholar 

  10. A.C. Adams, Dielectric and polysilicon film deposition, in VLSI Technology, 2nd ed. In S.M. Sze (ed.), McGraw Hill, New York, p. 251 (1988) and also N. Matsuki, J. Ohta, H. Fujika, M. Oshima, M. Yoshimoto, and H. Koinuma, Fabrication of oxide gate thin film transistors using PECVD/PLD multichamber system, Sci. Tech. Adv. Maters., 1, 187 (2000)

    Google Scholar 

  11. T. Hara and K. Sakata, Electrochem. Solid State Lett., 4, G-77 (2001)

    Google Scholar 

  12. Y.S. Kim, and Y. Shimogaki, J. Vac. Sci. Technol., A-192642 (2001)

    Google Scholar 

  13. S. Gandikota et al., Microelectron. Eng., 50, 547 (2000)

    Article  Google Scholar 

  14. O.K. Kwon, J.H. Kim, H.S. Park, and S.W. Kang, Atomic layer deposition of ruthenium thin film for copper glue layer, J. Electrochem. Soc., 151 (2), G-109 (2004)

    Article  Google Scholar 

  15. A.L.S. Loke, Process integration issues of low-permittivity dielectrics with copper for high performance interconnects, Ph.D. thesis, Stanford University, March, (1999)

    Google Scholar 

  16. Motorola XCM63R836RS3.3 M SRAM copper metallization Report: The chipworks Inc. Ottawa, ON, CA (1998)

    Google Scholar 

  17. S.P. Murarka and R.J. Gutmann, Advanced multilayer metallization schemes with Cu as interconnection metal, Thin Solid Films, 236, 257 (1993)

    Article  Google Scholar 

  18. R. Solanki and B. Pathangey, Electrochem. Solid State Lett., 3, 479 (2000) and T.P. Mofat, D. Wheeler, M.D. Edlestein, and D. Jossel, Superconformal film growth: Mechanism and quantification, IBM J. Res. Dev., 49 (1) (2005) and also M. Stewart et al., Interconnect patterning in a single step with multilevel nanoimprint lithography, VLSI multilevel interconnect Conf. (VMIC) October, (2005)

    Google Scholar 

  19. J.M. Steigerwald, S.P. Murarka, and R.J. Guttman, Chemical Mechanical Planarization, Wiley, New York, (1977)

    Google Scholar 

  20. J. Gotzlich and H. Rysell, Tapered windows in SiO2 and Si3N4 and polysilicon layers by ion implantation, J. Electrochem. Soc., 128, 617 (1981)

    Article  Google Scholar 

  21. W. Kern and R.S. Roster, Advances in the deposition processes for passivation films, J. Vac. Sci. Technol., 14, 1082 (1977)

    Article  Google Scholar 

  22. L.K. White, Bi-layer etching of fixed oxide and passivation layers, J. Electrochem. Soc., 127, 2687 (1980) and also S.N. Wolf and R.N. Tauber, Silicon Processing, Lattice Press, Sunset Beach, CA, Vol. 1, pp. 185–189 (1986)

    Google Scholar 

  23. G. Nanz and L.E. Camilletti, Modeling of chemical mechanical polishing: A review, IEEE Trans. Semiconductor manufacturing, 8 (4) Nov. (1995) and also P.Y. Wu and F.C. Chou, Complete analytical solutions of film planarization during semicoating, J. Electrochem. Soc., 146 (10), 3819 (1999)

    Google Scholar 

  24. D.B. Tuckerman and A.H. Weisberg, IEEE Electron Dev. Lett., EDL-7, 1 (1986)

    Google Scholar 

  25. T.S. Magee, J.S. Osborne, P. Gildea, and C.H. Leung, U.S. Patent No. 4758533, July 19, (1988) and also E. Ong, H. Chu, and S. Chen, Metal planarization with an excimer laser, Solid State Technol., 63, Aug (1991)

    Google Scholar 

  26. P. Wrschka, J. Hernandez, G.S. Oehrlein, and J. King, Chemical mechanical planarization of copper damascene structures, J. Electrochem. Soc., 147 (2), 706 (2000)

    Article  Google Scholar 

  27. M. Stell et al., Characterization of chemical mechanical planarization processes, In S.P. Murarka et al., (ed.), MRS Pub. Washington DC., (1994) and L. Lang, Modeling CMP for copper dual damascene interconnects, Solid State Technol., 111 June (2000)

    Google Scholar 

  28. F.B. Kaufman, D.B. Thompson, R.E. Broadier, M.A. Jaso, and W.L. Guthrie, J. Electrochem. Soc., 138, 3460 (1991) and L. Karuppiah et al., CMP-MIC Tech Dig. Feb., 45 (2006)

    Google Scholar 

  29. J. Tichy, J.A. Livert, L. Shan, and S. Danyluk, Contact mechanics and lubrication hydrodynamics of CMP, J. Electrochem. Soc., 146 (4), 1533 (1999) and also J.M. Steigerwald, S.P. Murarka, and R.J. Guttman, Chemical mechanical planarization of microelectronic materials, John Wiley, New York, (1997)

    Google Scholar 

  30. Y. Homma et al., Control of photocorrosion in copper damascene process, J. Electrochem. Soc., 147 (3), 1193 (2000) and A.B. Kahng, Adv. Met. Conf. UC Berkeley, Sept 22 (2008)

    Google Scholar 

  31. S. Sundararajan et al., Two dimensional wafer-scale chemical mechanical planarization models based on lubrication theory and mass transport, J. Electrochem. Soc., 146 (2), 761 (1999) and also T. Nakamura, K. Akamatsu, and N. Arakawa, Bull. Jpn. Soc. Precis. Eng., 19, 120 (1985)

    Google Scholar 

  32. W.T. Tseng and Y.L. Wang, Re-examination of pressure and speed dependencies of removal rate during chemical mechanical polishing processes, J. Electrochem. Soc., 144 (2) (1997)

    Google Scholar 

  33. W.J. Patrick et al., Application of chemical mechanical polishing to the fabrication of VLSI interconnects, J. Electrochem. Soc., 138, 1778–1784 (1991)

    Article  Google Scholar 

  34. P.A. Burke, Porch. IEEE 8th Int. VLSI interconnect. Conf. (VMIC), Santa Clara, CA, p. 379, June 11–12 (1991)

    Google Scholar 

  35. C. Lou et al., Dishing effects in CMP planarization process for advanced trench isolation, Appl. Phys. Letts., 61, 1344 (1992) and also J. Yu Lai, N. Saka, and J.H Chun, Evolution of copper-oxide structure in chemical mechanical polishing, J. Electrochem. Soc., 149 (1) G41 (2002)

    Google Scholar 

  36. C. You, A. Lulus, M. Grief, and T.T. Dan, Porch. IEEE, VLSI Multilevel Interconnect. Con., Santa Clara, CA, p. 156, (1992) and also J. Warnock, J. Chem. Soc., 138, 2398 (1991) and F. Zhang, A. Busnaina, and G. Ahmadi, Particle adhesion and removal in chemical mechanical polishing and post CMP cleaning, J. Electrochem. Soc., 146 (7), 2665 (1999) and also M. Sugiyamal, K. Ishikawa, M. Nakaishi, K. Yamashita and T. Ohba, Adv. Met Conf. The University of Tokyo, Japan, Sept 26 (2006)

    Google Scholar 

  37. J. You Al, N. Aka, and J.H. Chop, Evolution of copper-oxide damascene structures in CMP, Contact mechanics modeling, J. Chem. Soc., 149 (1) G-031 (2002)

    Google Scholar 

  38. T. Vo, T. Buley, and J.J. Gagliardi, Improved planarization for STI, Solid State Technol. (SST), 123 (June 2000) and also J.Y. Lai, N. Saka, and J.H. Chun, J. Electrochem. Soc., 149, G-31 (2002)

    Google Scholar 

  39. G.B. Basim, J.J. Adler, U. Mahajan, and B.M. Moudgil, Effect of particle size of CMP slurries for enhanced polishing with minimal defects, J. Electrochem. Soc., 147(9), 3523–3528 (2000)

    Article  Google Scholar 

  40. A.S. Dublin and P.J. Goetz, J. Colloids Surf., 158, 343 (1999)

    Article  Google Scholar 

  41. D.J. Chen and B.S. Lee, J. Pattern planarization model of chemical mechanical polishing, Electrochem. Soc., 146, 3420 (1999)

    Article  Google Scholar 

  42. L. Shan, S. Danyluk, J.A. Levert, Interfacial pressure measurements at chemical mechanical polishing interfaces, In S.V. Babu et al. (eds.) Chemical mechanical polishing, fundamental challenges, Proc. MRS., 187 (1999)

    Google Scholar 

  43. S.R. Runnels and P. Renteln, Dielectric Sci. Technol., 110, (1993) and also S.R. Runnels, F. Miceli, and I. Kim, Validation of a large area three dimensional erosion simulation for chemical mechanical polishing, J. Electrochem. Soc., 146 (12), 4619 (1999)

    Google Scholar 

  44. D. Wang, J. Lee, K. Holland, T. Bibby, and T. Cale, J. Electrochem. Soc., 141, 2843 (1997)

    Google Scholar 

  45. J. Warnock, J. Electrochem. Soc., 138, 2398 (1991) and T. Park, et al., Proc. 4th Int. Chem. Mech. For ULSI multilevel Interconnection Conf., CMP-MIC, Santa Clara, CA, p. 184 (1999)

    Google Scholar 

  46. P.T. Liu et al., Improvement of post CMP characteristics on organic low K MSQ as IMD, J. Electrochem. Soc., 147 (11) 4313–4317 (2000)

    Article  Google Scholar 

  47. Y. Feng et al., Corrosion mechanisms and products of copper in aqueous solutions at various pH values, Corrosion, 53 (5), 389 (1997)

    Article  Google Scholar 

  48. K. Kobayashi, K. Shimizu, G.E. Thompson, and G.E. Wood, Direct observation of the mosaic structure thermal oxide films on copper, Revue de metallurgie, 90 (12), 1627 (1993)

    Google Scholar 

  49. S.V. Babu, Y. Li, and A. Jindal, Chemical mechanical planarization of Cu and Ta, J. Materials (JOM), 50, March (2001)

    Google Scholar 

  50. S. Lassig, S. McClatchie, and A. Kiermasz, Selective removal of strategies for low-K dual damascene, Sem. Fab. Tech., 185 (2003)

    Google Scholar 

  51. S. Aksu and F.M. Doyle, Electrochemistry of copper in chemical mechanical planarization (CMP) slurries containing glycene and hydrogen peroxide, in Chemical mechanical planarization V, PV-2002-1, In S. Seal (ed.), The Electrochem. Soc. Pub. Pennington, NJ, (2002)

    Google Scholar 

  52. P. Suphantharida and K.O. Asare, Cerium oxide slurries in chemical mechanical polishing electrophoretic mobility and adsorption investigations of ceria/silicate interactions, J. Electrochem. Soc., 151 (10), G-658 (2004)

    Article  Google Scholar 

  53. K.O-Asare and K.K. Mishra, J. Electronic Mater., 25, 1599 (1996), and also H. Hirabayashi, M. Huguchi, M. Kinoshita, H. Haysaka, K. Mase, and J. Oshim, US Patent number 5575885 (1996)

    Google Scholar 

  54. Q. Luo, D.R. Campbell, and S. Babu, Thin Solid Films, 311, 177 (1997)

    Article  Google Scholar 

  55. Q. Luond and S.V. Babu, Dishing effects during CMP of copper in acid media, J. Electrochem. Soc., 147(12) 4639–4644 (2000)

    Article  Google Scholar 

  56. A.S. Dukhin and P.J. Goetz, Colloid Surf. A, 158, 343 (1999) and E.E. Ramsen et al., J. Electrochem. Soc., 153, G453 (2006)

    Google Scholar 

  57. S. Kondo et al., Abrasive free polishing for copper damascene interconnections, J. Electrochem. Soc., 147(10) 3907–3913 (2000)

    Article  Google Scholar 

  58. S.P. Murarka, Advanced metallization for devices and circuits science and technology and manufacturability, MRS Pub. Philadelphia, PA, (1994) and also R. Jairath et al., Solid State Technol., 107 Oct. (1996) and Z. Stavreva, D. Zeidler, M. Plotner, and K. Drescher, Characterization in chemical mechanical polishing of copper: Comparison of polishing pads, Appl. Surf. Sci., 108, 39 (1997)

    Google Scholar 

  59. J.J. Colacine et al., Analysis of velocity as a cause of thickness variations in a CMP process, Solid State Technol., 30 (Aug 1973) and also C. Rogers, J. Coppeta, L. Racz, and D. Bramono, Analysis of flow between a wafer and pad during CMP processes, J. Electron. Mater., 27 (10), 1082 (1998) and also Y. Li et al., 23rd Int Conf. on VLSI/ULSI Multilevel Interconnect, Sept-26, (2006)

    Google Scholar 

  60. O.G. Checknia, L.M. Keer, and H. Liang, J. Electrochem. Soc., 145, 2100 (1998)

    Article  Google Scholar 

  61. J.U. Lai, N. Saka, and J.H. Chun, Evolution of copper damascene in chemical mechanical polishing, Electrochem. Soc., 199 (1), G31–G40 (2002)

    Article  Google Scholar 

  62. T. Yu et al., A statistical polishing pad model for CMP, Proc. IEEE Int. Electron Dev., (1993) and also S.H. Ng, R. Height, C. Zhou, I. Yoon, and S. Danyluk, Pad soaking effect on interfacial fluid pressure measurements during CMP, J. Tribology, 125 (3), 582 (2003)

    Google Scholar 

  63. L.A. Galin, In contact problems in the theory of elasticity translated by H. Moss and I. Snedon, (eds.) N.C. State College Raleigh, NC, (1961) and also D. Wang, J. Lee, K. Holland, T. Bibby, and T. Cale, J. Electrochem. Soc., 141, 2843 (1997) and Y. Li et al., 23rd Int. Symp. on VLSI/ULSI multilevel interconnect, Sept. 26 (2006)

    Google Scholar 

  64. Y. Homma et al., Control of photocorrosion in the copper damascene process, J. Electrochem. Soc., 147 (3) 1193 (2000)

    Article  MathSciNet  Google Scholar 

  65. J.M. Steigerwald et al., Chemical mechanical planarization of microelectronics materials, Wiley, New York, (1997)

    Book  Google Scholar 

  66. J.J. Gagliardi, STI polishing with 3 M’s fixed abrasive, 16th Intl. VLSI multilevel interconnection Conf. pp. 223–228 (1999) and B. Lee, D.S. Boeing, and L. Economikos, Proc. CMP-MIC Conf., Santa Clara, CA, p. 395 (2001)

    Google Scholar 

  67. M. Fayolle, J.F. Lugandi, F. Weimar and W. Bruxvoort, Proceedings of the CMP-MIC Conf., San Diego CA, p. 128 (1998) and also T. Park, T. Tugabaw, D. Boeing, S, Hymes, T. Brown, K. Samekalin, and G. Schwartz, In Chemical Mechanical Polishing in IC Device Manufacturing, III, In R.L. Olipa et al. (eds.), Electrochem. Soc. Pub. Pennington, NJ (1999)

    Google Scholar 

  68. U. Mahajan, M. Bielman, and R. Singh, Mater. Res. Soc Pub., Pittsburgh, PA, Vol. 566 (1999)

    Google Scholar 

  69. L. Doyen, D. Vacher, K. Tarutani, R. Bouard, F. Picore, and D. Girad, Analysing large particles in CMP slurries, Semcond. Intl., p. 75, (August, 2002) and also R.S. Subramanian and R.M. Appat, Electrochem. Solid State Letts., 4 (12), G-115 (2001)

    Google Scholar 

  70. P. Wrschka, J. Hernandez, G.S. Oehrlein and J. King, Chemical mechanical planarization of copper damascene structures, J. Electrochem. Soc., 147(2), 706–712 (2000) and Y. Uozumi et al., IEEE IITC, p. 25 June (2007)

    Article  Google Scholar 

  71. N. Toyama, Copper impurity levels in silicon, Solid State Electron., 26 (1), 37 (1997)

    Article  MathSciNet  Google Scholar 

  72. J.M. Steigerwald, R. Zirpoli, S.P. Murarka, D. Price, and R.J. Gutmann, J. Electrochem. Soc., 141, 2842 (1994)

    Article  Google Scholar 

  73. J.M. Fayolle and F. Romagna, Microelectron. Eng., 37/38, 135 (1997)

    Article  Google Scholar 

  74. Z. Stavreva, D. Zeidler, M. Ploetner, and K. Drescher, Appl. Surf. Sci., 108, 39 (1997)

    Article  Google Scholar 

  75. J.U. Lai, N. Saka, and J.H. Chun, Evolution of copper damascene in chemical mechanical polishing, Electrochem. Soc., 199 (1), G31–G40 (2002) and also K. Witt and L. Cook, Getting an edge with CMP, Semicond. Int. p. 74 Oct. (2000)

    Google Scholar 

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Gupta, T. (2009). The Copper Damascene Process and Chemical Mechanical Polishing. In: Copper Interconnect Technology. Springer, New York, NY. https://doi.org/10.1007/978-1-4419-0076-0_6

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