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Deposition Technologies of Materials for Cu-Interconnects

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Copper Interconnect Technology

Scaling of the feature size from 250 nm to sub-100 nm has restricted the use of aluminum (Al) interconnects. At the same time demands for higher speed, better performance of the scaled circuits, and thinner gate material need better dielectric materials other than silicon dioxide (SiO2). As a result, copper has replaced Al-interconnect and low-K interlayer and high-K gate dielectric materials have replaced SiO2. Deep submicron copper interconnects cannot be formed by using the conventional cloisonné approach which is ubiquitous in Al metallization. Experimental evidence shows that dry etching of Cu is difficult and photoresist work cannot withstand the temperatures required for Cu-etching (>200 ºC). Moreover, wet etching and lift-off techniques of Cu have been attempted without much success. So a new process technology known as the damascene process has been introduced to integrate Cu-interconnects in modern integrated circuits (ICs).

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Gupta, T. (2009). Deposition Technologies of Materials for Cu-Interconnects. In: Copper Interconnect Technology. Springer, New York, NY. https://doi.org/10.1007/978-1-4419-0076-0_5

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