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Pattern Generation

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Copper Interconnect Technology

The desire for small feature size continues to make tremendous gains in device performance but with added circuit complexity. Fine pattern generation on the deposited dielectric layer is the usual practice in damascene (single/dual) architecture. The main driver behind this is advanced photolithography (or lithography which uses a high polymer, called a resist, and a proper radiative exposure with proper optical systems). In an effort to keep up the trend of reduction in feature size, semiconductor industries have switched over from conventional ultraviolet (UV) to deep ultraviolet (DUV) lithography. Figure 4.1 shows a picture of the trenches produced by using DUV resist and phase-shift mask (PSM). The resist images show a k 1 factor as small as 0.25 (the 2004 ITRS requirement for technology node is hp90 and is expected to be hp65 by the year 2007, where hp 90 means 90 nm node technology).

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    Tapan Gupta

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Gupta, T. (2009). Pattern Generation. In: Copper Interconnect Technology. Springer, New York, NY. https://doi.org/10.1007/978-1-4419-0076-0_4

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