This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
Bibliography
B. K. Ahuja, “An Improved Frequency Compensation Technique for CMOS Operational Amplifiers”, Journal of Solid-State Circuits, Vol. SC-18, pp. 629–633, November 1983.
L. A. Akerst, “An Analytical Expression for the Threshold Voltage of a Small Geometry MOSFET”, Solid State Electronics, Vol. 24, pp. 621–627, 1981.
M. Annaratone, “Digital CMOS Circuit Design”, Kluwer Academic Publishers.
H. Arakawa, “Address Decoder Circuit for Non-Volatile Memory”, United States Patents 5,039,882, August 13, 1991.
S. Aritome, “Advance Flash Memory Technology and Trends for File Storage Application”, in IEDM Tech. Dig., pp. 763–766, 2000.
S. Aritome, R. Shirota, G. Hemink, T. Endoh, F. Masoka, “Reliability Issues of Flash Memory Cells”, Proc. IEEE, Vol. 81, No. 5, pp. 776–788, May 1993.
S. Atsumi et al., “A 3.3V-only 16 Mb Flash Memory with Row-Decoding scheme”, 1996 IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, pp. 42–43, February 1996.
S. Atsumi et al., “A Channel-Erasing 1.8 V-Only 32-Mb NOR Flash EEPROM with a Bitline Direct Sensing Scheme”, IEEE Journal of Solid-State Circuits, Vol. SC-35, pp. 1648–1654, November 2000.
C. Auricchio et al., “A Triple-Well Architecture for Low Voltage Operation in Submicron CMOS Devices”, (Eds.), Proc. ESSDERC 96, Bologna, Italy, p. 613, 1996.
M. Bauer et al., “A multilevel-cell 32 Mb Flash Memory”, in 1995 IEEE Int. Solid-State Circuits Conf. Dig. Tech.Pap., pp. 132–133, February 1995.
H.P. Belgal et al., “A New Reliability Model for Post-cycling Charge Retention of Flash Memories”, Proc. IRPS, pp. 7–20, 2002.
A. Bellaouar et al., “Bootstrapped Full-Swing BiCMOS/BiNMOS Logic Circuits for 1.2–3.3 V Supply Voltage Regime”, IEEE Journal of Solid-State Circuits, Vol. 30, No. 6, June 1995.
R. Bez, "Introduction to Flash Memory”, IEEE Proceeding of the, Vol. 91, No. 4, pp. 489–502, April 2003.
R. Bez et al., “Depletion Mechanism of Flash Cell Induced by Parasitic Drain Stress Contid-ion”, VLSI Technology Symposium, 1994.
R. Bez et al., “Introduction to Flash Memory”, Proceedings of the IEEE, Vol. 91, pp. 554–568, 2003.
C. S. Bill el al., High Voltage Charge Pumps with Series Capacitances, USA Patent No. 5,059,815.
A. Brand et al., “Novel Read Disturb Failure Mechanism Induced by FLASH Cycling”, IEEE IRPS, 1993.
W. D. Brown, J. E. Brewer, eds., “Nonvolatile Semiconductor Memory Technology”, New York, NY: IEEE Press, 1998.
G. Campardo, R. Micheloni, “Row Decoder for a Flash-EEPROM Memory Device with the Possibility of Selective Erasing of a Sub-Group of Rows of a Sector”, USA Patent No. 6,122,200.
G. Campardo, R. Micheloni, “Architecture of Non Volatile Memory with Multi-bit Cells”, 12th Bi-annual Conference June 20–23, INFOS2001, Invited paper, 2001.
G. Campardo, R. Micheloni, “Architecture of Non volatile Memory with Multi-Bit Cells”, Elsevier Science, Microelectronic Engineering, Vol. 59, No. 1-4, pp. 173–181, November 2001.
G. Campardo, R. Micheloni, “Scanning the Special Issue on Flash Memory Technology”, IEEE Proceeding of the, Vol. 91, No. 4, pp. 483–488, April 2003.
G. Campardo, R. Micheloni, S. Commodaro, “Line Decoder for Memory Devices”, USA Patent No. 6,018,255.
G. Campardo, R. Micheloni, S. Commodaro, “Low Supply Voltage Nonvolatile Memory Device with Voltage Boosting”, USA Patent No. 5,903,498.
G. Campardo, R. Micheloni, S. Commodaro, “Method and Circuit for Reading Low-Supply-Voltage Nonvolatile Memory Cells”, USA Patent No. 6,128,225.
G. Campardo, R. Micheloni, M. Maccarrone, “Circuit and Method for Generating a Read Reference Signal for Nonvolatile Memory Cells”, USA Patent No. 5,805,500.
G. Campardo, R. Micheloni, M. Maccarrone, “Read Circuit and Method for Nonvolatile Memory Cells with an Equalizing Structure”, USA Patent No. 5,886,925.
G. Campardo, R. Micheloni, D. Novosel “VLSI-Design of Non-volatile Memories”, Springer Series in ADVANCED MICROELECTRONICS, 2005.
G. Campardo et al., “Method and Circuit for Dynamic Reading of a Memory Cell at Low Supply Voltage and with Low Output Dynamics”, USA PatentNo. 6,639,833.
G. Campardo et al., “Method and Circuit for Generating an ATD Signal to Regulate the Access to a Non-volatile Memory”, USA Patent No. 6,075,750.
G. Campardo et al., “A 40 mm2 3V 50 MHz 64 Mb 4-level Cell NOR Type Flash Memory”, 2000 ISSCC, San Francisco.
G. Campardo et al., “Circuit Structure for Providing a Hierarchical Decoding in Semiconductor Memory Devices”, USA PatentNo. 6,515,911.
G. Campardo et al., “40- 3-V-only 50-MHz 64-Mb 2-b/cell CHE NOR Flash Memory”, IEEE Journal of Solid-State Circuits, Vol. SC-35, No. 11, pp. 1655–1667, November. 2000.
G. Campardo et al., “An overview of Flash Architectural Developments”, IEEE Proceeding of the, Vol. 91, No. 4, pp. 523–536, April 2003.
P. Cappelletti, A. Modelli, "Flash Memory Reliability”, in Flash Memory, P. Cappelletti et al., Ed Kluwer, 1999.
P. Cappelletti et al., Eds., “Flash Memories”, Norwell, MA: Kluwer, 1999.
E. Charbon, R. Gharpurey, P. Miliozzi, R. G. Meyer, A. Sangiovanni-Vincentelli, “SUBSTRATE NOISE – Analysis and Optimization for IC design”, Kluwer Academic Publishers, 2001.
R. L. M. Dang, N. Shigyo, “Coupling Capacitance for Two-Dimensional Wires”, IEEE Electron Deviced Letters, Vol. EDL-2, No. 8, pp. 196–197, August 1981.
S. D’arrigo et al., “A 5V-Only 256K Bit CMOS Flash EEPROM”, ISSCC 89, pp. 132–133.
S. H. Dhong et al., “High Speed Sensing Scheme for CMOS DRAM’s”, IEEE Journal of Solid-State Circuits, Vol. 23, No. 1, pp. 34–40, February 1988.
G. Di Cataldo, G. Palumbo, “Double and Triple Charge Pump for Power IC Dynamic Models Which Take Parasitic Effects into Account”, IEEE Transaction Circuits System, Vol. CAS-40, pp. 92–101, February 1993.
J. Dickson, “On-Chip High Voltage Generation in MNOS Integrated Circuits Using an Improved Voltage Multiplier Technique”, IEEE Journal of Solid-State Circuits, Vol. SC-11, No. 3, pp. 374–378, June 1976.
C. Dunn et al., “Flash EEPROM Disturb Mechanisms”, in Proc. Int. Rel. Phys. Symp., pp. 299–308, April 1994.
B. Eitan and D. Frohman-Bentchkowski, “Hot Electron Injection into the Oxide in n-channel MOS Devices”, IEEE Trans. Electron Devices, Vol. ED-28, pp. 328–340, March 1981.
D. Elmhurst et al., “A 1.8 V 128 Mb 125 MHz Multi-level Cell Flash Memory with Flexible Read While Write”, ISSCC Dig. Tech. Papers, pp. 286–287, February 2003.
D. Frohman-Bentchkowsi, “Memory Behavior in a Floating Gate Avalanche-Injection MOS (FAMOS) Structure”, Appl. Phys. Lett., Vol. 18, pp. 332–334, 1971.
D. Frohman-Bentchkowsi, “FAMOS-A New Semiconductor Charge Storage Device”, Solid State Electron, Vol. 17, pp. 517–520, 1974.
G. Ginami. et al., “Survey on Flash Technology with Specific Attention to the Critical Process Parameters Related to Manufacturing”, IEEE Proceeding of the, Vol. 91, No. 4, pp. 503–522, April 2003.
P. R. Gray, R.G. Meyer, “MOS Operational Amplifier Design- A Tutorial Overview”, IEEE Journal of Solid State Circuits, Vol. SC-17, No. 6, pp. 969–982, December 1982.
R. Gregorian, G. C. Temes, Analog Mos Integrated Circuits for Signal Processing, J. Wiley & Sons, 1986.
M. Grossi et al., “Program Schemes for Multilevel Flash Memories”, IEEE Proceeding of the, Vol. 91, No. 4, pp. 594–601, April 2003.
S. S. Haddadi et al., Flash E2PROM Array with Negative Gate Voltage Erase Operation, U.S. Patent No. 5,077,691, October 23, 1989.
T. P. Haraszti, CMOS Memory Circuits. Boston, MA: Kluwer Academic Publishers, Ch. 5, 2000.
H. Hidaka et al., “Twisted Bit-Line Architectures for Multi-Megabit DRAM’s”, IEEE Journal of Solid-State Circuits, Vol. 24, No. 1, pp. 21–27, February 1989.
M. Horiguchi, M. Aoki, Y. Nakagome, S. Ikenaga, K. Shimohigashi, “An Experimental Large-Capacity Semiconductor File Memory Using 16-Levels/Cell Storage”, IEEE Journal of Solid-State Circuits, Vol. 23, No. 1, pp. 27–33, February 1988.
C. Hu, “Lucky-Electron Model for Channel Hot-Electron Emission”, 1979 IEDM Tech. Dig., pp. 22–25, December 1979.
C. Hu, “Future CMOS Scaling and Reliability”, Proceedings of the IEEE, Vol. 81, pp. 682–689, 1993.
IEEE 1995, Nonvolatile Semiconductor Memory Workshop, “Flash Memory Tutorial”, Monterey, California, August 14, 1995.
IEEE Standard Department, “IEEE P1005 draft standard for definitions, symbols, and char-acteristics of floating gate memory arrays”, approved 1998.
D. Ielmini, A.S. Spinelli, A.L. Lacaita, L. Confalonieri, A. Visconti, “New technique for Fast Characterisation of SILC Distribution in Flash Arrays”, Proc. IRPS, pp. 73–80, 2001.
D. Ielmini, A.S. Spinelli, A.L. Lacaita, R. Leone, A. Visconti, “Localisation of SILC in Flash Memories after Program/Erase Cycling”, Proc. IRPS, pp. 1–6, 2002.
D. Ielmini, A. Spinelli, A. Lacaita, A. Modelli, “Statistical Model of Reliability and Scaling Projections for Flash Memories”, IEDM Tech. Dig., 2001.
T. S. Jung et al., “A 3.3-V 128-Mb Multilevel NAND Flash Memory for Mass Storage Applications”, in ISSCC Dig. Tech. Papers, pp. 32–33, February 1996.
T. Kawahara et al., “Bit-Line Clamped Sensing Multiplex and Accurate High-Voltage Generator for 0.25 $μ $M Flash Memories”, in 1996 IEEE Int. Solid-State Circuits Conf. Dig. Tech. Pap., pp. 38–39, February 1996.
S. Keeney, “A 130 nm Generation High-Density ETOX Flash Memory Technology”, IEDM Tech. Dig., p. 41, 2001.
S. Kenney et al., “Complete Transient Simulation of Flash EEPROM Devices”, IEEE Transaction on Electron Devices, Vol. 39, pp. 2750–2757, 1992.
O. Khouri, S. Gregori, R. Micheloni, D. Soltesz, G. Torelli, “Low Output Resistance Charge Pump for Flash Memory Programming”, 2001 IEEE Proc. Int. Workshop on Memory Technology, Design and Testing, San Jose, CA (USA), pp. 99–104, August 2001.
O. Khouri, S. Gregori, A. Cabrini, R. Micheloni, G. Torelli, “Improved Charge Pump for Flash Memory Applications in Triple-Well CMOS Technology”, in 2002 IEEE Proc. Int. Symposium on Industrial Electronics, L’Aquila (Italy), pp. 1322–1326, July 2002.
O. Khouri, R. Micheloni, S. Gregori, G. Torelli, “Fast Voltage Regulator for Multilevel Flash Memories”, in Records 2000 IEEE Int. Workshop on Memory Technology, De-sign and Testing, pp. 34–38, August 2000.
O. Khouri, R. Micheloni, I. Motta, A. Sacco, G. Torelli, “Capacitive Boosting Circuit for the Regulation of the Word Line Reading Voltage in Non-Volatile Memories”, U.S. Patent No. 6.259.635.
O. Khouri, R. Micheloni, I. Motta, G. Torelli, “Word-Line Read Voltage Regulator with Capacitive Boosting for Multimegabit Multilevel Flash Memories”, in Proc. European Conf. Circuit Theory and Design 1999, Vol. I, pp. 145–148, August–September 1999.
O. Khouri, R. Micheloni, A. Sacco, G. Campardo, G. Torelli, “Program Word-Line Voltage Generator for Multilevel Flash Memories”, in Proc. 7th IEEE Int. Conf. on Elec-tronics, Circuits, and Systems, Vol. II, pp. 1030–1033, December 2000.
O. Khouri, R. Micheloni, G. Torelli, “Very Fast Recovery Word-Line Voltage Regulator for Multilevel Non-volatile Memories”, in Proc. Third IMACS/IEEE Int. Multiconfer-ence Circuits, Communications and Computers, Athens, Greece, pp. 3781–3784, June 1999.
Y. Konishi et al., “Analysis of Coupling Noise Between Adjacent Bit Lines in Megabit DRAM’s”, IEEE Journal of Solid-State Circuits, Vol. 24, No. 1, February 1989.
V. N. Kynett et al., “An In-System Reprogrammable 256 K CMOS Flash Memory”, ISSCC, Conf. Proc., pp. 132–133, 1988.
V. N. Kynett et al., “A 90-ns one-million Erase/Program Cycle 1-Mbit Flash memory”, IEEE Journal of Solid-State Circuits, Vol. SC-24, pp. 1259–1264, October 1989.
M. Lenzlinger, E. H. Show, “Fowler-Nordheim Tunnelling into Thermally Grown SiO2”, IEDM Technical Digest, Vol. 40, pp. 273–283, 1969.
M. Maccarrone et al., “Program Load Adaptive Voltage Regulator for Flash Memories”, Journal of Solid-State Circuit, Vol. 32, No. 1, p. 100, January 1997.
S. Mahapatra, S. Shukuri, J. Bude, “CHISEL Flash EEPROM–Part I: Performance and Scaling”, IEEE Trans. Electron Devices, Vol. ED-49, pp. 1296–1301, July 2002.
F. Maloberti, “Analog Design for CMOS VLSI System”, Kluwer Academic Publishers, Boston, 2001.
T. Mano, J. Yamada, J. Inoue, and S. Nakajima, “Circuit Techniques for a VLSI Memory”, IEEE Journal of Solid-State Circuits, Vol. 18, No. 5, pp. 463–469, October 1983.
S. Maramatsu et al., “The solution of Over-Erase Problem Controlling Poly-Si Grain Size-Modified Scaling Principles for Flash Memory”, IEDM Tech. Dig., pp. 847–850, 1994.
M. McConnel et al. , “An Experimental 4-Mb Flash EEPROM with Sector Erase”, IEEE Journal of Solid-State Circuits, Vol. 26, No. 4, pp. 484–489, April 1991.
R. Micheloni et al., “Row Decoder Circuit for an Electronic Memory Device, Particularly for Low Voltage Applications”, USA PatentNo. 6,069,837.
R. Micheloni et al., “Line Decoder for a Low Supply Voltage Memory Device”, USA PatentNo. 6,111,809.
R. Micheloni et al., “Nonvolatile Memory Device, in Particular a Flash-EEPROM”, USA PatentNo. 6,351,413.
R. Micheloni et al., “Method and a Related Circuit for Adjusting the Duration of a Synchronization Signal ATD for Timing the Access to a Non-volatile Memory”, USA Patent No. 6,075,750.
R. Micheloni et al., “Method for Reading a Multilevel Nonvolatile Memory and Multilevel Nonvolatile Memory”, USA Patent No. 6,301,149.
R. Micheloni et al., “Read Circuit for a Nonvolatile Memory”, USA Patent No. 6,327,184.
R. Micheloni, M. Zammattio, G. Campardo, O. Khouri, G. Torelli, “Hierarchical Sector Bi-asing Organization for Flash Memories”, in Records 2000 IEEE Int. Workshop on Memory Technology, Design and Testing, pp. 29–33, August 2000.
R. Micheloni, I. Motta, O. Khouri, G. Torelli, “Stand-by Low-Power Architecture in a 3-V only 2-bit/cell 64-Mbit Flash Memory”, in Proc. 8th IEEE Int. Conf. Electronics, Circuits, and Systems, Vol. II, pp. 929–932, September 2001.
R. Micheloni, I. Motta, O. Khouri, G. Torelli, "Stand-by Low-Power Architecture in a 3-V only 2-bit/cell 64-Mbit Flash Memory”, inProc. 8th IEEE Int. Conf. Electronics, Circuits, and Systems, Vol. II, pp. 929–932, September 2001.
R. Micheloni et al., “A 0.13-$μ $m CMOS NOR Flash Memory Experimental Chip for 4-b/cell Storage”, ESSCIRC 28th Proc. European Solid-State Circuit Conf., pp. 131–134, September 2002.
R. Micheloni et al. , “The Flash Memory Read Path Building Blocks and Critical Aspects”, IEEE Proceeding of the, Vol. 91, No. 4, pp. 537–553, April 2003.
M. Mihara, Y. Terada, M. Yamada, “Negative Heap Pump for Low Voltage Operation Flash Memory”, in 1996 Symposium VLSI Circuits Dig. Tech. Pap., pp. 76–77, June 1996.
K. Ming-Dou, W. Chung-Yu, W. Tain-Shun, “Area-Efficient Layout Design for CMOS Output Transistors”, IEEE, Trans. On Electron Devices, Vol. 44, No. 4, April 1997.
Y. Miyawaki et al., “A New Erasing and Row Decoding Scheme for Low Supply Voltage Operation 16-Mb/64-Mb Flash Memories”, IEEE Journal of Solid State Circuits, Vol. 27, No. 4, April 1992.
Y. Mochizucki, “Read-Disturb Failure in Flash Memory at Low Field”, Intel reports, Nikkei Electronics Asia, pp. 35–36, May 1993.
A. Modelli, R. Bez, A.Visconti “Multi-level Flash Memory Technology”, 2001 Interna-tional Conference on Solid State Devices and Materials (SSDM), Tokyo, Extended Abstract, pp. 516–517, 2001.
A. Modelli, A. Manstretta, G. Torelli, “Basic Feasibility Constraints for Multilevel CHE-Programmed Flash Memories”, IEEE Transaction Electron Devices, Vol. ED-48, pp. 2032–2042, September 2001.
S. Mori et al., “ONO Interpoly Dielectric Scaling for Non-Volatile Memories Applications”, IEEE Trans. On Electron Devices, Vol. 38, No. 2, pp. 386–391, 1991.
H. Morimura, N. Shibata, “A Step-Down Boosted-Wordline Scheme for 1-V Battery-Operated Fast SRAM’s”, IEEE Journal of Solid-State Circuits, Vol. SC-33, No. 8, August 1998.
I. Motta, G. Ragone, O. Khouri, G. Torelli, R. Micheloni, “High-Voltage Management in Single-Supply CHE NOR-Type Flash Memories”, Proceedings of the IEEE, Vol. 91, pp. 554–568, 2003.
S. Mukherjee, T. Chang, R. Pang, M. Knecht, D. Hu, “A Single Transistor EEPROM Cell and its Implementation in a 512 K CMOS EEPROM”, IEDM Tech. Dig., pp. 616–619, 1958.
K. Natori, “Sensitivity of dynamic MOS Flip-Flop Sense Amplifiers”, IEEE Transaction on Electron Devices, Vol. ED-33, No. 4, pp. 482–488, April 1986.
M. Ohkawa el al., “A 9.8 mm 2 Die size 3.3 V 64 Mb Flash Memory with FN-NOR type Four Level Cell”, IEEE Journal of Solid-State Circuit, Vol. 31, No. 11, p. 1584, November 96.
N. Otsuka, M. A. Horowitz, “Circuit Techniques for 1.5-V Power Supply Flash Memory”, IEEE Journal of Solid-State Circuits, Vol. 32, No. 8, August 1997.
P. Pavan, R. Bez, P. Olivo, E. Zanoni, "Flash Memory Cells – An Overview”, Proceedings of the IEEE, Vol. 85, pp. 1248–1271, 1997.
A. Pierin, S. Gregori, O. Khouri, R. Micheloni, G. Torelli, "High-Speed Low-Power Sense Comparator for Multilevel Flash Memories” in Proc. 7th Int. Conf. Electronics, Circuits and Systems, Vol. II, pp. 759–762, December 2000.
B. Prince, “Semiconductor Memories. A Handbook of Design Manufacture and Appli-cation”, Wiley & Sons, 1993.
D. B. Ribner, M. A. Copeland, Design Techniques for Cascode CMOS Op Amps with Im-proved PSRR and Common Mode Input Range, IEEE Journal of Solid-State Circuits, Vol. SC-19, No. 6, pp. 919–925, December 1984.
B. Riccò et al., “Nonvolatile Multilevel Memories for Digital Applications”, Proc. IEEE, Vol. 86, pp. 2399–2421, December 1998.
G. A. Rincon-Mora, P. E. Allen, “A Low-Voltage, Low Quiescent Current, Low Drop-out Regulator”, IEEE Journal of Solid-State Circuits, Vol. SC-33, pp. 36–44, January 1998.
P. L. Rolandi et al., “A 32 Mb-4b/cell Analog Flash Memory Supporting Variable Density with Only Supply and serial I/O”, 25th ESSCIRC 99.
P. L. Rolandi et al., “1M-cell 6b/cell Analog Flash Memory for Digital Storage”, IEEE ISSCC Dig. Tech. Papers, pp. 334–335, February 1998.
T. Sakurai, K. Tamaru, “Single Formulas for Two-and Three-Dimensional Capacitances”, IEEE Transactions on Electron Devices, Vol. ED-30, No. 2, pp. 183–185, February 1983.
L. Selmi, C. Fiegna, “Physical Aspects of Cell Operation And Reliability”, in Flash Memory, P. Cappelletti et al., Ed Norwell, Ma: Kluwer, 1999.
A. Silvagni et al., “Modular Architecture For a Family of Multilevel 256/192/128/64Mb 2-Bit/Cell 3V Only NOR FLASH Memory Devices”, ICECS 2001, Malta, September 2001.
S. M. Sze, “Physics of Semiconductor Device”, John Wiley & Sons, Inc, New York, 1969.
Y. Tang et al., –Different Dependence of Band-to-Band and Fowler-Nordheim Tunneling on Source Doping Concentration of an n-MOSFET”, IEEE Electron Device Letters, Vol. 17, p. 525, 1996.
T. Tanzawa, S. Atsumi, “Optimization of Word-Line Booster Circuits for Low-Voltage Flash Memories”, IEEE Journal of Solid-State Circuits, Vol. SC-34, pp. 1091–1098, August 1999.
T. Tanzawa, T. Tanaka, “A Dynamic Analysis of the Dickson Charge Pump Circuit”, IEEE Journal of Solid-State Circuits, Vol. SC-32, No. 8, pp. 1231–1240, August 1997.
U. Tietze, CH. Schenk, “Advanced electronic circuit”, Springer-Verlag Berlin Heidelberg New York, 1978.
A. Umezawa et al., (1992), “A 5 V-only Operation 0.6-um Flash EEPROM with Row Decoder Scheme in Triple-Well Structure”, IEEE Journal of Solid-State Circuits, Vol. 27, pp. 1540–1546.
S. T. Wang, “On the I-V Characteristics of Floating-Gate Mos Transistors”, IEEE Transaction on Electron Devices, Vol. ED-26, No. 9, September 1979.
C. C. Wang, J. Wu, “Efficiency Improvement in Charge Pump Circuits”, IEEE Journal of Solid-State Circuits, Vol. SC-32, pp. 852–860, June 1997.
M. Zammattio, I. Motta, R. Micheloni, C. Golla, “Low Consumption Voltage Boost Device”, U.S. Patent No. 6.437.636.
M. Zhang. N. Llaser, F. Devos, “Improved Voltage Tripler Structure with Symmetrical Stacking Charge Pump”, Electronics Letters, Vol. 37, pp. 668–669, May 2001.
Author information
Authors and Affiliations
Rights and permissions
Copyright information
© 2008 Springer-Verlag Berlin Heidelberg
About this chapter
Cite this chapter
Micheloni, R., Marelli, A., Ravasio, R. (2008). NOR Flash memories. In: Error Correction Codes for Non-Volatile Memories. Springer, Dordrecht. https://doi.org/10.1007/978-1-4020-8391-4_3
Download citation
DOI: https://doi.org/10.1007/978-1-4020-8391-4_3
Publisher Name: Springer, Dordrecht
Print ISBN: 978-1-4020-8390-7
Online ISBN: 978-1-4020-8391-4
eBook Packages: EngineeringEngineering (R0)