Conclusion

ESD has been considered as a major reliability threat in semiconductor industry for decades. As CMOS technology scales down, design of ESD protection circuits becomes more challenging. This is due to thinner gate oxides, shallower junction depths, and smaller channel lengths in advanced technologies that make them more vulnerable to ESD damages. As a result, design window for the ESD protection circuit becomes narrower. The design window is often interpreted as the voltage difference between the avalanche breakdown voltage (V_t1) and gate oxide breakdown voltage. For example, in 90 nm technology, the gate oxide breakdown voltage under ESD conditions is only 1 V above the drain junction breakdown voltage which leaves only 1 V design window for the ESD protection circuit. Furthermore, scaling of CMOS technology is often accompanied by increase in operating frequency, increase in total chip area, and number of packaged pins. Higher operating frequency sets a limit on the maximum parasitic capacitance of the ESD protection circuit for packaged pins. At the same time, increase in the number of pads limits the available area for ESD protection circuits. As a result, considerable effort is needed to meet the speed requirements, while satisfying the area and robustness requirements of the ESD protection circuits.