In previous chapters, we discussed design of ESD protection circuits with respect to device and circuit parameters. Similarly, most of the ESD related publications are focused on these aspects as well. However, ESD circuit parameters do influence the design parameters of circuit to be protected. Therefore, the interaction between ESD protection circuit and the main circuit is another challenge that should be studied carefully. This issue is becoming very important as circuits are moving towards higher frequencies and higher data rates since ESD parasitics may affect the performance of these circuits.
An ESD protection circuit adds extra parasitic capacitance to the main circuit. This capacitance is mainly reverse biased pn junction capacitance, which is highly non-linear. As a result, an ESD protection circuit can degrade both frequency response and linearity performance of the main circuit. The former, which is due to mere presence of the parasitic capacitance, has been well understood. However, the latter, which is due to non-linear behavior of the junction capacitance, hasn’t been discussed in detail. In this chapter, the main focus is on the impact of ESD protection on high performance circuits. Hence, in Section 2 parasitic capacitance asso ciated with different ESD protection circuits is presented. In Sections 3 to 5 three different case studies are discussed and impact of ESD protection circuits on their respective performance is examined. The first two are on the impact of ESD protection circuit on linearity of analog to digital converters (ADCs), while the last one reports the impact of ESD protection on jitter of current mode logic (CML) drivers.
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(2008). ESD Protection Circuits for High-Speed I/OS. In: ESD Protection Device and Circuit Design for Advanced CMOS Technologies. Springer, Dordrecht. https://doi.org/10.1007/978-1-4020-8301-3_6
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