Circuit Design Concepts for ESD Protection

The internal ESD protection requires the placement of adequate on-chip protection devices on the I/O and on the power supply pins to reliably bypass the ESD energy before it can damage the sensitive circuits. The onchip protection scheme should have an explicit and robust path for the ESD currents to flow between any pair of pins. In general, pad protection networks shunt I/O pins to the ground or V_DD bus under stress events. For each input pin, a dedicated protection network, that is completely passive under normal operating conditions, has to be added. For each output pin, the ESD protection level is determined by the intrinsic robustness of the output buffer transistors plus that of the dedicated protection devices. A good protection element should minimize the nominal performance and/or voltage degradation to the I/O circuit due to its insertion and provide a low-impedance shunt path for the ESD current. The protection element must be capable of handling multiple ESD events without itself being destroyed. It should also not interfere with the I/O circuit during its normal operation. Hence, a perfect protection device should have the following characteristic:

• Very low on-resistance

• Triggering voltage should be above the worst case operating supply voltage (V_DD + 10%)

• Almost instantaneous turn-on time

• Very high energy handling capability

• Only trigger during ESD events, not during normal operation

• Very low parasitics to minimize performance degradation of I/O circuit

• Consumes small area

Very low on-resistance allows it to shunt large amount of current with no voltage rise from an ohmic voltage drop. It is clear that a real ESD protecttion device can not have all of these characteristics, but these criteria provide a list of optimizations and compromises to be struck when the protection circuit is designed.