One of the most observed sources of electrostatic charge is the shock caused by touching a doorknob after walking in a carpeted room. This shock is a result of discharging the body’s accumulated charge through a conductive object. Normally, this electrostatic discharge can be a few kilo-volts. In semiconductor industry the discharge path can be through semiconductor devices. Before going through the details of this phenomenon in semiconductor devices, a brief review of static electricity is necessary.
Static electricity is the creation of electrical charge by an imbalance of electrons on the surface of a material which produces an electrical field. When two objects with different electrical potentials are brought in contact, a charge transfer occurs between these two objects. This phenomenon is called electrostatic discharge. There are different ways to create a charge on a material: triboelectric charging, induction, ion bombardment and contact with another charged object. The most common mechanism is triboelectric charging. Triboelectric charging is the creation of charge by the contact and separation of two materials. Consider contact and separation of two uncharged materials. As a result, based on the nature of materials, electrons transfer from one material to the other. Therefore, material that looses electrons becomes positively charged while the other material becomes negatively charged. The amount of this triboelectric charge depends on many factors such as area of contact, speed of separation and relative humidity. Table 1-1 shows some examples of the amount of generated electrostatic charge under different conditions and for two different relative humidity situations. It can be seen that higher humidity reduces the generated charge significantly. Electrostatic discharge occurs when this charge is transferred to another material. The resistance of the actual discharge circuit and the contact resistance at the interface between contacting surfaces determines the charge that can cause damage.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
S. U. Kim, “ESD induced gate oxide damage during wafer fabrication process,” EOS/ESD Symposium, pp. 99–105, 1992.
R. G. Chemelli, B. A. Unger, and P. R. Bossard, “ESD by static induction,” EOS/ESD Symposium, pp. 29–36, 1983.
C. Diaz, S. M. Kang, and C. Duvvury, “Tutorial electrical overstress and electrostatic discharge,” IEEE Trans. on Reliability, vol. 44, No. 1, pp. 2–5, 1995.
J. Bernier and G. Groft, “Die level CDM testing duplicates assembly operation failures,” EOS/ESD Symposium, pp. 117–122, 1986.
C. Russ, ESD Protection Devices for CMOS Technologies: Processing Impact, Modeling, and Testing Issues, Ph.D. thesis, 1999.
J. -B. Huang and G. Wang, “ESD protection design for advanced CMOS,” Proc. of SPIE, vol. 4600, pp. 123–131, 2001.
J. E. Vinson and J. J. Liou, “Electrostatic discharge in semiconductor devices: protection techniques,” Proc. of the IEEE, vol. 88, No. 12, pp. 1878–1900, 2000.
H. A. Gieser, “ESD testing: HBM to very fast TLP”, tutorial presented at the ISREF 2004.
D. W. Greve, “Programming mechanism of polysilicon resistor fuses,” IEEE Trans. Electron Dev., vol. ED-29, No. 4, pp. 719–724, 1982.
D. Pierce, “Electrostatic discharge (ESD) failure mechanisms,” EOS/ESD Symposium, Tutorial Notes, pp. C-1–C-32, 1995.
A. Wang, “On-chip ESD protection design: mixed-mode simulation and ESD for RF/mixed-signal ICs,” tutorial presented at the BCTM 2003.
C. Duvvury and A. Amerasekera, “ESD: a pervasive reliability concern for IC techno logies,” Proc. of the IEEE, vol. 81, No. 5, pp. 690–702, 1993.
ITRS 2005, Factory Integration Chapter, Electrostatic Discharge - Backup Section: Details and Assumptions for Technology Requirements, http://www.itrs.net/Links/2005ITRS/Linked%20Files/2005Files/Factory/ElectroStatic%20Discharge%20Backup05RevFINAL.ppt
W. Russell, “Defuse the threat of ESD damage,” Electronic Design, vol. 43, No 5, pp. 115–120, 1995.
M. Song, D. C. Eng, and K. P. MacWilliams, “Quantifying ESD/EOS latent damage and integrated circuit leakage currents,” EOS/ESD Symposium, pp. 304–310, 1995.
R. Renninger, M. Jon, D. Ling, et al. “A field induced charged-device model simulator,” EOS/ESD Symposium, pp. 59–71, 1989.
S. H. Voldman, “The impact of technology scaling on ESD robustness of aluminum and copper interconnects in advanced semiconductor technologies,” IEEE Trans. on Components, Packaging & Manufacturing Technology, Part C (Manufacturing), vol. 21, No. 4, pp. 265–277, 1998.
D. K. Kontos, R. Gauthier, D. E. Ioannou, T. Lee, Min Woo, K. Chatty, C. Putnam, and M. Muhammad, “Interaction between electrostatic discharge and electromigration on copper interconnects for advanced CMOS technologies,” Proc. of the Int. Reliability Physics Symp. (IRPS), pp. 91–97, 2005.
C. -K. Hu, B. Luther, F. B. Kaufman, J. Hummel, C. Uzoh, and D. J. Pearson, “Copper interconnection integration and reliability,” Thin Solid Films, vol. 262, No. 1–2, pp. 84–92, 1995.
S. H. Voldman, “The impact of technology evolution and scaling on electrostatic discharge (ESD) protection in high-pin count high-performance microprocessors,” IEEE Int. Solid-State Cir. Conf. (ISSCC), pp. 366–367, 1999.
S. H. Voldman, “A review of electrostatic discharge (ESD) in advanced semiconductor technology,” Microelectronics Reliability, vol. 44, No. 1, pp. 33–46, 2004.
Semiconductor Industry Association (SIA), “The National Technology Roadmap for Semiconductors,” 2005.
S. Voldman, “High-current characterization of dual-damascene copper interconnects in SiO2- and low-k interlevel dielectrics for advanced CMOS semiconductor technologies,” Proc. of the Int. Reliability Physics Symp. (IRPS), pp. 144–153, 1999.
W. Fichtner, K. Esmark, and W. Stadler, “TCAD software for ESD on-chip protection design,” Proc. of the Int. Electron Devices Meeting (IEDM), pp. 14.1.1–14.1.4, 2001.
H. Gossner, “ESD protection for the deep sub micron regime – a challenge for design methodology,” Proc. of the Int. Conf. on VLSI Design (VLSID), pp. 809–818, 2004.
Rights and permissions
Copyright information
© 2008 Springer Science+Business Media B.V.
About this chapter
Cite this chapter
(2008). Introduction. In: ESD Protection Device and Circuit Design for Advanced CMOS Technologies. Springer, Dordrecht. https://doi.org/10.1007/978-1-4020-8301-3_1
Download citation
DOI: https://doi.org/10.1007/978-1-4020-8301-3_1
Publisher Name: Springer, Dordrecht
Print ISBN: 978-1-4020-8300-6
Online ISBN: 978-1-4020-8301-3
eBook Packages: EngineeringEngineering (R0)