Abstract
Test Methodologies for Globally Asynchronous Locally Synchronous (GALS) System On a Chip (SOC) are a subject of growing research interest since they appear to offer benefits in low power applications and promise greater design modularity. Pre-designed cores and reusable modules are popularly used in the design of large and complex Systems. As the size and complexity of System increase, the test effort, including test development effort, test data volume, and test application time, has also significantly increased. Available techniques for testing of core-based systems on a chip do not provide a systematic means for compact test solutions. A test solution for a complex system requires good optimization of Test Scheduling and Test Access Mechanism (TAM). In this paper, we provide a Test Scheduling Optimization for Globally Asynchronous Locally Synchronous System-On-Chip Using Genetic Algorithm that gives compact test scheduling.
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References
S. Chattopadhyay and K. Sudharsana Reddy, “Genetic Algorithm Based Test Scheduling and Test Access Mechanism Design for System-On-Chips”, Proceedings of the International Conference on VLSI Design, 2003.
Vikram Iyengar, K. Chakrabarthy and Erik. J. Marinissen, “Efficient Wrapper/TAM Co – Optimization for Large SOCs”, http://www.ee.duke.edu/∼ krish/237_iyengar_v.pdf
Erik Jan Marinissen, V. Iyengar and K.Chakrabarthy,“A Set of Benchmarks for Modular Testing of SOCs”, http://www.extra.research.philips.com/itc02socbenchm
Martin Keim, Nicole Drechsler, Rolf Drechsler and Brend Becker, “Combining GAs and Sysmbolic Methods for High Quality Tests of Sequential Circuits”, Journal of Electronic Testing: Theory and Applications, Vol. 17, 2001, pp 37-51.
Srivaths Ravi, Ganesh Lakshminarayana and Niraj. K. Jha, “Testing of Core-Based Systems-on-a-Chip”, IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, Vol. 20, No. 3, 2001, pp. 426-439.
Erik Larsson, Klas Arvidsson, Hideo Fujiwara and Zebo Peng, “Efficient Test Solutions for Core-Based Designs”, IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, Vo. 23, No. 5, 2004, pp. 758-774.
Anuja Sehgal, V. Iyengar and K. Chakrabarthy, “SOC Test Planning Using Virtual Test Access Architectures”, IEEE Transactions on Very Large Scale Integration Systems, Vo. 12, No. 12, 2004, pp. 1263 – 1276.
Yuejian Wu and Paul MacDonald, “Testing ASIC with Multiple Identical Cores”, IEEE Transactions on Computer Aided Design of Integarated Circuits and Systems, Vo. 22, No. 3, 2003, pp. 327 – 336.
V. Iyengar, A. Chandra, S. Schweizer and K. Chakrabarthy, “A Unified Approach for SOC Testing Using Test Data Compression and TAM Optimization”, Proceedings of the Design, Automation and Test in Europe Conference and Exhibition, 2003.
Cheng-Wen Wu, “SOC Testing Methodology and Practice”, Proceedings of the Design, Automation and Test in Europe Conference and Exhibition, 2005.
Aristides Efthymiou, John Bainbridge and Douglas Edwards, “Adding Testability to an Asynchronous Interconnect for GALS SOC”, Proceedings of the 13 th Asian Test Symposium, 2004.
Hemangee K. Kapoor and Mark B. Josephs,“Modelling and Verification of delay-insensitive circuits using CCS and the Concurrency Workbench”, Information Processing Letters, Vo. 89, 2004, pp.293-296.
Eunjung OH, Soo-Hyun Kim, Dong-Ik Lee and Ho-Yong Choi, “High Level Test Generation for Asynchronous Circuits from Signal Transition Graph”, IEICE Transactions on Fundamentals, Vo.E85-A, No. 12, 2002, pp. 2674 – 2683.
Yin-He SU, Ching-Hwa CHENG and Shih-Chieh CHANG, “Novel Techniques for Improving Testability Analysis”, IEICE Transactions on Fundamentals, Vol. E85-A, No. 12, 2002, pp. 2901-2912.
Mathew Sacker, Andrew D. Brown, Andrew J. Rushton and Peter R. Wilson, “A Behavioral Synthesis System for Asynchronous Circuits”, IEEE Transactions on Very Large Scale Integration Systems, Vol.12, No.9, 2004, pp. 978 – 994.
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Sakthivel, P., Narayanasamy, P. (2007). An Approach to the Design of Optimal Test Scheduling for System-On-Chip Based on Genetic Algorithm. In: Sobh, T. (eds) Innovations and Advanced Techniques in Computer and Information Sciences and Engineering. Springer, Dordrecht. https://doi.org/10.1007/978-1-4020-6268-1_5
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DOI: https://doi.org/10.1007/978-1-4020-6268-1_5
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