Design Criteria for Cyclic and Pipelined ADCs

This chapter focuses on system level design of algorithmic type ADCs which can be either cyclic or pipelined. Firstly, the ADC is reviewed at an algorithmic and system level. Next, the effects of hardware constraints on ADC accuracy are critically examined with specific attention paid to static and dynamic performance. The effects of errors on the ADC transfer characteristic are simulated and error bounds derived. Finally, those specific design issues affecting pipelined ADCs are examined. The performance of a pipelined ADC can be enhanced via the use of a multi-bit front-end stage and analogue hardware scaling down the remaining low-resolution back-end stages. This is critically analysed. Finally, a model is proposed to estimate the power per stage and hence total power consumption of the pipelined ADC.