Multi-processor System-on-Chip (MPSoC) architectures in future will be implemented in less than 50 nm technology and include tens to hundreds of processing element blocks operating in the multi-GHz range. The on-chip interconnection network will be a key factor in determining the performance and power consumption of these multi-core devices. Packet switched interconnection networks or Network-on-Chip (NoC) has emerged as an attractive alternative to traditional bus-based architectures for satisfying the communication requirements of these MPSoC architectures. The key challenge in NoC design is to produce a complex, high performance and low energy architecture under tight time to market requirements. The NoC architectures would support the communication demands of hundreds of cores under stringent performance constraints. In addition to the complexity, the NoC designers would also have to contend with the physical challenges of design in nanoscale technologies. The NoC design problem would entail a joint optimization of the system-level floorplan and power consumption of the network. All these factors coupled with the requirement for short turn around times raises the need for an intellectual property (IP) re-use methodology that is well supported with design and optimization techniques, and performance evaluation models. This chapter introduces the concept of NoC and presents the various elements of the IP-based system-level methodology required for its design.
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References
SIA. International Technical Roadmap for Semiconductors. Technicalreport, http://public.itrs.net/, 2004.
D. Sylvester and K. Keutzer. A Global Wiring Paradigm for Deep Submi-cron Design. IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, pages 242-252, February 2000.
R. Ho, K. Mai, and M. Horowitz. The Future of Wires. In Proceedings of IEEE, pages 490-504, April 2001.
J. Davis and D. Meindl. Compact Distributed RLC Interconnect Models - Part I: Single Line Transient, Time Delay and Overshoot Expressions. IEEE Transactions on Electron Devices, 47(11):2068-2077, November 2000.
J. Davis and D. Meindl. Compact Distributed RLC Interconnect Models - Part II: Coupled Line Transient Expressions and Peak Crosstalk in Mul-tilevel Networks. IEEE Transactions on Electron Devices, 47(11):2078-2087, November 2000.
D. Sylvester and K. Keutzer. Impact of Small Process Geometries on Microarchitectures in Systems on a Chip. In Proceedings of the IEEE, pages 467-484, April 2001.
A. Hemani, A. Jantsch, S. Kumar, A. Postula, J. Oberg, and M. Millberg. Network on Chip: An Architecture for Billion Transistor Era. In Pro-ceedings of IEEE NorChip Conference, November 2000.
M. Sgroi, M. Sheets, A. Mihal, K. Keutzer, S. Malik, J. Rabaey, and A. Sangiovanni-Vincentelli. Addressing the System-on-a-Chip Interconnect Woes Through Communication-Based Design. In Proceedings of Design Automation Conference, pages 667-672, June 2001.
L. Benini and G. De-Micheli. Networks on Chips: A New SoC Paradigm. IEEE Computer, pages 70-78, January 2002.
W.J. Dally and B. Towles. Route Packet, Not Wires: On-Chip Intercon-nection Networks. In Proceedings of DAC, June 2002.
N. Banerjee, P. Vellanki, and K.S. Chatha. A Power and Performance Model for Network-on-Chip Architectures. In Proceedings of DATE, Paris, France, February 2004.
Krishnan Srinivasan, Karam S. Chatha, and Goran Konjevod. “Lin-ear Programming based Techniques for Synthesis of Network-on-Chip Architectures”. Accepted for IEEE Transactions on VLSI, 2006.
A. Jalabert, S. Murali, L. Benini, and G. De-Micheli. xpipesCompiler: A Tool for Instantiating Application Specific Networks on Chip. In DATE, 2004.
J. Duato, S. Yalamanchili, and L. Ni. Interconnection Networks, an Engineering Approach. IEEE Computer Society, 1997.
P. Sotiriadis and A. Chandrakasan. A Bus Energy Model for Deep Sub-micron Technology. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 10(3):341-350, June 2002.
Clark N. Taylor, Sujit Dey and Yi Zhao. Modeling and Minimization of Interconnect Energy Dissipation in Nanometer Technologies. In Proceedings of DAC, June 2001.
M.B. Taylor, J. Kim, J. Miller, D. Wentzlaff, F. Ghodrat, B. Greenwald, H. Hoffman, P. Johnson, J.-W. Lee, W. Lee, A. Ma, A. Saraf, M. Seneski, N. Shnidman, V. Strumpen, M. Frank, S. Amarasinghe, and A. Agrawal. The RAW Microprocessor: A Computational Fabric for Software Circuits and General-Purpose Programs. IEEE Micro, pages 25-35, March-April 2002.
Chi-Hsiang Yeh, Emmanouel A. Varvarigos, and Behrooz Parhami. Mul-tilayer VLSI Layout for Interconnection Networks. In International Conference on Parallel Processing, pages 33-40, 2000.
Ronald I. Greenberg and Lee Guan. On the Area of Hypercube Layouts. Information Processing Letters, 84(1):41-46, 2002.
Shimon Even and Roni Kupershtok. Layout Area of the Hypercube: (Extended Abstract). In SODA ’02: Proceedings of the Thirteenth Annual ACM-SIAM Symposium on Discrete Algorithms, pages 366-371, Philadelphia, PA, USA, 2002. Society for Industrial and Applied Mathe-matics.
Chi-Hsiang Yeh, Emmanouel A. Varvarigos, and Behrooz Parhami. Efficient VLSI Layouts of Hypercubic Networks. In Proceedings of Symposium on Frontiers of Massively Parallel Computation, pages 98-105, February 1999.
Andre DeHon. Multilayer Layout for Butterfly Fat-Tree. In Twelfth Annual ACM Symposium on Parallel Algorithms and Architectures, July 2000.
S.M. Sait and H. Youssef. VLSI Physical Design Automation: Theory and Practice. McGraw-Hill Inc, 1994.
P. Chen, and E.S. Kuh. Floorplan Sizing by Linear Programming Approximation. In Proceedings of DAC, Los Angeles, California, June 2000.
J.G. Kim, and Y.D. Kim. A Linear Programming Based Algorithm for Floorplanning in VLSI Design. IEEE Transactions on CAD, 22(5), 2003.
W.J. Dally and C.L. Seitz. Deadlock-free Message Routing in Multi-Processor Interconnection Networks. IEEE Transactions on Computers, C-36(5):547-553, 1987.
J. Hu and R. Marculescu. Energy-Aware Mapping for Tile-based NoC Architectures Under Performance Constraints. In ASP-DAC, 2003.
Krishnan Srinivasan and Karam S. Chatha. A Technique for Low Energy Mapping and Routing in Network-on-Chip Architectures. In Proceedings of International Symposium in Low Power Electronic Design, San Diego, CA, August 2005.
C.M. Fiduccia and R.M. Mattheyses. A Linear-Time Heuristic for Improving Network Partitions. In Proceedings of DAC, 1982.
Naveed Sherwani. Algorithms for VLSI Physical Design Automation. Kluwer Academic Publishers, 1995.
A. Leon-Garcia and I. Widjaja. Communication Networks, Fundamental Concepts and Key Architectures. McGraw Hill, 2000.
H.J. Seigel. A Model of SIMD Machines and a Comparison of Var-ious Interconnection Networks. IEEE Transactions on Computers, 28(12):907-917, December 1979.
L.N. Bhuyan (editor). Special Issue: Interconnection Networks. IEEE Computer, June 1987.
W.J. Dally. Performance Analysis of k-ary n-cube Interconnection Net-work. IEEE Transactions on Computers, 39(6):775-785, June 1990.
J.F. Draper and J. Ghosh. A Comprehensive Analytical Model for Worm-hole Routing in Multicomputer Systems. Journal of Parallel and Distributed Computing, 23:202-214, 1994.
W.B. Ligon III and U. Ramachandran. Towards a More Realistic Perfor-mance Evaluation of Interconnection Networks. IEEE Transactions on Parallel and Distributed Systems, 8(7):681-694, July 1997.
A. Andriahantenaina and A. Greiner. Micro-Network for SoC: Imple-mentation of a 32-Port SPIN Network. In DATE, Munich, Germany, March 2003.
A. Andriahantenaina, H. Charlery, A. Greiner, L. Mortiez, and C. A. Zeferino. SPIN: A Scalable, Packet Switched, on-Chip MicroNetwork. In DATE, Munich, Germany, March 2003.
D. Siguenza-Tortosa and J. Nurmi. Proteo: A New Approach to Network-on-Chip. In Proceedings of IASTED International Conference on Communication Systems and Network, Malaga, Spain, 2002.
Mikael Millberg, Erland Nilsson, Rikard Thid, Shashi Kumar, and Axel Jantsch. The Nostrum Backbone - A Communication Protocol Stack for Networks on Chip. In VLSI Design Conference, Mumbai, India, January 2004.
Mikael Millberg, Erland Nilsson, Rikard Thid, and Axel Jantsch. Guar-anteed Bandwidth Using Looped Containers in Temporally Disjoint Networks within the Nostrum Network on Chip.. In DATE, pages 890-895, February 2004.
John Dielissen, Andrei R ădulescu, Kees Goossens, and Edwin Rijpkema. Concepts and Implementation of the Philips Network-on-Chip. In IPBased SOC Design, November 2003.
E. Rijpkema, K.G.W. Goossens, and A. Radulescu. Trade Offs in the Design of a Router with Both Guaranteed Best-Effort Services for Networks on Chip. In DATE, 2004.
Praveen Vellanki, Nilanjan Banerjee, and Karam S. Chatha. Quality of Service and Error Control Techniques for Network-on-Chip Architectures. In Proceedings of IEEE Great Lakes Symposium on VLSI (GLSVLSI), Boston, MA, April 2004.
Praveen Vellanki, Nilanjan Banerjee, and Karam S. Chatha. “Quality-of-Service and Error Control Techniques for Mesh based Network-on-Chip Architectures”. Integration, The VLSI Journal, 38:353-382, January 2005.
H. Zimmer and A. Jantsch. A Fault Model Notation and Error-Control Scheme for Switch-to-Switch Buses in a Network-on-Chip. In ISSS/CODES, 2003.
F. Worm, P. Ienne, P. Thiran, and G. De Micheli. An Adaptive Low-Power Transmission Scheme for On-Chip Networks. In Proceedings of ISSS, Kyoto, Japan, 2002.
X. Chen and L-S Peh. Leakage Power Modeling and Optimization in Interconnection Networks. In Proceedings of ISLPED, Seoul, Korea, 2003.
E. Nilsson and J. Oberg. Reducing Power and Latency in 2-D Mesh NoC Using Globally Pseudochronous and Locally Synchronous Clocking. In Proceedings of ISSS-CODES, 2004.
David Brooks, Vivek Tiwari, and Margaret Martonosi. Wattch: a Frame-work for Architectural-Level Power Analysis and Optimizations. In International Symposium on Computer Architecture, pages 83-94, 2000.
W. Ye, N. Vijaykrishna, M. Kandemir, and M.J. Irwin. The Design and Use of SimplePower: A Cycle-Accurate Energy Estimation Tool. In Proceedings of Design Automation Conference, June 2000.
D. Pamunuwa, J. Oberg, L.R. Zheng, M. Millberg, A. Jantsch, and H. Tenhunen. Layout, Performance and Power Trade-Offs in Meshbased Network-on-Chip Architectures. In IFIP International Conference on Very Large Scale Integration(VLSI-SOC), Darmstadt, Germany, pages 362-367, December 2003.
Evgeny Bolotin, Israel Cidon, Ran Ginosar, and Avinoam Kolodny. Cost Considerations in Network-on-Chip. In Integration - the VLSI journal, November 2003.
T.T. Ye, L. Benini, and G. De Micheli. Analysis of Power Consumption on Switch Fabrics in Network Routers. In Proceedings of DAC, 2002.
H.-S. Wang, L.-S. Peh, and S. Malik. Orion: A Power-Performance Simulator for Interconnection Network. In International Symposium on Microarchitecture, Istanbul, Turkey, November 2002.
J. Chan and S. Parameswaran. “NoCEE: Energy Macro-Model Extraction Methodology for Network-on-Chip Routers”. In Proceedings of Interna-tional Conference on Computer-Aided Design, San Jose, CA, November 2005.
J. Hu and Radu Marculescu. Exploiting the Routing Flexibility for Energy/Performance Aware Mapping of Regular NoC Architectures. In DATE, 2003.
S. Murali and G. De Micheli. Bandwidth-Constrained Mapping of Cores onto NoC Architectures. In DATE, 2004.
G. Ascia, V. Catania, and M. Palesi. Multi-Objective Mapping for Mesh-based NoC Architectures. In Proceedings of ISSS-CODES, 2004.
K. Srinivasan, K.S. Chatha, and Goran Konjevod. Linear Program-ming based Techniques for Synthesis of Network-on-Chip Architectures. In Proceedings of IEEE International Conference on Computer Design (ICCD), San Jose, USA, October 2004.
Krishnan Srinivasan and Karam S. Chatha. SAGA: Synthesis Tech-nique for Guaranteed Throughput NoC Architectures. In Proceedings of ACM/IEEE Asia-South Pacific Design Automation Conference (ASP-DAC), Shanghai, China, January 2005.
S. Murali, L. Benini, and G. De Micheli. Mapping and Physical Planning of Networks-on-Chip Architectures with Quality-of-Service Guarantees. In Proceedings of ASPDAC, 2005.
U.Y. Ogras and R. Marculescu. Energy- and Performance-Driven NoC Communication Architecture Synthesis Using a Decomposition App-roach. In Proceedings of DATE, Munich, Germany, 2005.
Krishnan Srinivasan, Karam S. Chatha, and Goran Konjevod. An Auto-mated Technique for Topology and Route Generation of Application Spe-cific on-Chip Interconnection Networks. In Proceedings of International Conference on Computer-Aided Design, San Jose, CA, November 2005.
K. Srinivasan and K.S. Chatha. A Low Complexity Heuristic for Design of Custom Network-on-Chip Architectures. In Proceedings of Design Automation and Test in Europe, Munich, Germany, March 2006.
A. Pinto, L. P. Carloni, and A.L. Sangiovanni-Vincentelli. Efficient Syn-thesis of Networks on Chip. In ICCD, 2003.
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Chatha, K.S., Srinivasan, K. (2007). System-Level Design of Network-on-Chip Architectures. In: Henkel, J., Parameswaran, S. (eds) Designing Embedded Processors. Springer, Dordrecht. https://doi.org/10.1007/978-1-4020-5869-1_18
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