Abstract
This chapter completes the description and demonstration of the reuse-based design framework presented here. It basically delves into the why and how of including layout geometric information and layout-induced parasitics within the optimization loop of the cell-level sizing process. Outlined in Chapter 2, these sizing techniques, namely geometrically constrained sizing and parasitic- aware sizing, are now the object of the present chapter.
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© 2006 Springer
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CASTRO-LÓPEZ, R., FERNÁNDEZ, F., GUERRA-VINUESA, O., RODRÍGUEZ-VÁZQUEZ, Á. (2006). Layout-Aware Circuit Sizing. In: Reuse-Based Methodologies and Tools in the Design of Analog and Mixed-Signal Integrated Circuits. Springer, Dordrecht. https://doi.org/10.1007/978-1-4020-5139-5_7
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DOI: https://doi.org/10.1007/978-1-4020-5139-5_7
Publisher Name: Springer, Dordrecht
Print ISBN: 978-1-4020-5126-5
Online ISBN: 978-1-4020-5139-5
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