Abstract
This paper presents an efficient graph-based evolutionary optimization technique called Evolutionary Graph Generation (EGG), and its application to arithmetic circuit synthesis. Key features of EGG are to employ a graph-based representation of individuals and to manipulate the graph structures directly by evolutionary operations. The potential capability of EGG is demonstrated through experimental synthesis of arithmetic circuits with different levels of abstraction. Design examples include (i) combinational multipliers using word-level arithmetic components (such as parallel counters and parallel shifters), (ii) bit-serial multipliers using bit-level arithmetic components (such as 1-bit full adders and 1-bit registers), and (iii) multiple-valued current-mode arithmetic circuits using transistor-level components (such as current sources and current mirrors).
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References
Aoki, T. & Higuchi, T. (2000). Beyond-Binary Arithmetic – Algorithms and VLSI Implementations –. Interdisciplinary Information Sciences 6(1): 75–98.
Aoki, T., Homma, N. & Higuchi, T. (1999a). Evolutionary Design of Arithmetic Circuits. IEICE Trans. Fundamentals E82-A(5): 798–806.
Aoki, T., Sawada, Y. & Higuchi, T. (1999b). Signed-Weight Arithmetic and Its Application to a Field-Programmable Digital Filter Architecture. IEICE Trans. Electronics E82-C(9): 1687–1698.
Avizienis, A. (1961). Signed-Digit Number Representations for Fast Parallel Arithmetic. IRE Trans. Electronic Computers 10: 389–400.
Back, T., Hammel, U. & Schwefel, H. P. (1997). Evolutionary Computation: Comments on the History and Current State. IEEE Trans. Evolutionary Computation 1(1): 3–13.
Brent, P. R. & Kung, H. T. (1981). The Area-Time Complexity of Binary Multiplication. Journal of the Association for Computing Machinery 28(3): 521–534.
Degawa, K., Aoki, T. & Higuchi, T. (2003). A Field-Programmble Digital Filter Chip Using Multiple-Valued Current-Mode Logic. Proceedings 33rd IEEE Int’l Symp. MultipleValued Logic, 213–220.
Dempster, A. G. & Macleod, D. M. (1994). Constant Integer Multiplication Using Minimum Adders.IEE Proceedings Circuits Devices Syst. 141(5): 407–413.
Haddow, C. P. & Tufte, G. (2000). An Evolvable Hardware FPGA for Adaptive Hardware. Proceedings of the 2000 Congress on Evolutionary Computation, 553–560.
Hartley, R. I. (1996). Subexpression Sharing in Filters Using Canonic Signed Digit Multipliers. IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process. 43(10): 677–688.
Higuchi, T., Iwata, M., Keymeulen, D., Sakanashi, H., Murakawa, M., Kajitani, I., Takahashi, E., Toda, K., Salami, M., Kajihara, N. & Otsu, N. (1999). Real-World Applications of Analog and Digital Evolvable Hardware. IEEE Trans. Evolutionary Computation 3(3): 220–235.
Higuchi, T., Murakawa, M., Iwata, M., Kajitani, I. & Weixin, L. (1997). Evolvable Hardware at Function Level. Proceedings of the 1997 IEEE International Conference on Evolutionary Computation (ICEC ’97), 187–192.
Homma, N., Aoki, T. & Higuchi, T. (2000a). Evolutionary Graph Generation System with Symbolic Verification for Arithmetic Circuit Design. IEE Electronics Letters 36(11): 937–939.
Homma, N., Aoki, T. & Higuchi, T. (2000b). Evolutionary Synthesis of Fast Constantcoefficient Multipliers. IEICE Trans. Fundamentals E83-A(9): 1767–1777.
Homma, N., Aoki, T. & Higuchi, T. (2001). Evolutionary Graph Generation System with Transmigration Capability for Arithmetic Circuit Design. Proceedings of The 2001 IEEE International Symposium on Circuits and Systems 5 of 5, 171–174.
Huelsbergen, L., Rietman, E. & Slous, R. (1999). Evolving Oscillators in Silico. IEEE Trans. Evolutionary Computation 3(3): 197–204.
Hwang, K. (1979). Computer Arithmetic: Principles, Architecture, and Design. John Wiley & Sons.
Kameyama, M., Kawahito, S. & Higuchi, T. (1988). A Multiplier Chip with Multiple-Valued Bidirectional Current-Mode Logic Circuits. IEEE Computer 21(4): 43–56.
Kawahito, S., Kameyama, M. & Higuchi, T. (1990). Multiple-Valued Radix-2 Signed-Digit Arithmetic Circuits for High-Performance VLSI Systems. IEEE J. Solid-State Circuits 25(1): 125–131.
Kawahito, S., Kameyama, M., Higuchi, T. & Yamada, H. (1988). A 32 x 32-Bit Multiplier Using Multiple-Valued MOS Current-Mode Circuits. IEEE J. Solid-State Circuits 23(1): 124–132.
Khoo, K., Kwentus, A. & Willson, N. A. (1996). A Programmable FIR Digital Filter Using CSD Coefficients. IEEE J. Solid-State Circuits 31(6): 869–874.
Koren, I. (1993). Computer Arithmetic Algorithms. Prentice Hall.
Koza, R. J., Bennett, E H., Andre, D., Keane, M. A. & Dunlap, E (1997). Automated Synthesis of Analog Electrical Circuits by Means of Genetic Programming. IEEE Trans. Evolutionary Computation 1(2). 109–128.
Lohn, D. J. & Colombano, S. P. (1999). A Circuit Representation Technique for Automated Circuit Design. IEEE Trans. Evolutionary Computation 3(3): 205–219.
Miller, E J., Thomson, P. & Fogarty, T. (1997). Designing Electronic Circuits Using Evolutionary Algorithms. Arithmetic Circuits: A Case Study. Genetic Algorithms and Evolution Strategies in Engineering and Computer Science, 105–131.
Omondi, A. R. (1994). Computer Arithmetic Systems: Algorithms, Architecture and Implementations. Prentice Hall.
Thompson, A., Layzell, P. & Zebulum, R. S. (1999). Explorations in Design Space: Unconventional Electronics Design Through Artificial Evolution. IEEE Trans. Evolutionary Computation 3(3): 167–196.
Tyrrell, M. A., Hollingworth, G. & Smith, S. L. (2001). Evolutionary Strategies and Intrinsic Fault Tolerance. Proceeding of the 3rd NASA/DoD Workshop on Evolvable Hardware, 98–106.
Wallace, C. S. (1964). A Suggestion for a Fast Multiplier. IEEE Trans. Electron. Computer 13. 14–17.
Wong, B. C. & Samueli, H. (1991). A 200-MHz All-Digital QAM Modulator and Demodulator in 1.2-µm CMOS for Digital Radio Applications. IEEE Journal Solid-State Circuits 26(12): 1970–1979.
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Aoki, T., Homma, N., Higuchi, T. (2004). Evolutionary Synthesis of Arithmetic Circuit Structures. In: Artificial Intelligence in Logic Design. Artificial Intelligence in Logic Design, vol 766. Springer, Dordrecht. https://doi.org/10.1007/978-1-4020-2075-9_3
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DOI: https://doi.org/10.1007/978-1-4020-2075-9_3
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