Skip to main content
SpringerLink
Log in

Advanced BEOL Technology Overview

  • Chapter
  • First Online:
Advanced Nanoscale ULSI Interconnects: Fundamentals and Applications

Abstract

Performance interconnects degrade with shrinking dimensions of the ULSI device. The scaling rules below depict these dimensions. To develop high-performance ULSI devices, minimizing the RC delay of interconnects is crucial. Decreasing power dissipation is also critical for high-performance system-on-chip (SOC) devices.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Log in via an institution
Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 129.00
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 169.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD 169.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

References

  1. Shibata, H.: Chip-level Interconnect Scaling and Copper/Low-k Process Integrational Technology for 65 nm Node and beyond (invited). The Electrochemical Society of Japan, Proc. of the 67th Symposium on Semiconductors and Integrated Circuits Technology, 42–, 47 (2004)

    Google Scholar 

  2. Yoshimaru, M.; Koizumi, S.; and Shimokawa, K.: Structure of fluorine-doped silicon oxide films deposited by plasma-enhanced chemical vapor deposition. J. Vac. Sci. Technol. A 15 , 2908 (1997)

    Article  CAS  Google Scholar 

  3. Yoshimaru, M.; Koizumi, S.; and Shimokawa, K.: Interaction between water and fluorine-doped silicon oxide films deposited by plasma-enhanced chemical vapor deposition. J. Vac. Sci. Technol. A 15 , 2915 (1997)

    Article  CAS  Google Scholar 

  4. Steinlesberger, G.; Schindler, G.; Engelhardt, M.; Steinhogel W.; and Traving, M.: Aluminum Nano Interconnects. IEEE International Interconnect Technology Conference, 51–, 53 (2004)

    Google Scholar 

  5. Jiang, Q. T.; Tsai M. H.; and Havemann, R. H.: Line Width Dependence of Copper Reliability. IEEE International Interconnect Technology Conference, 227–, 229 (2001)

    Google Scholar 

  6. Schindler, G.; Steinhogel, W.; Steinlesberger, G.; Traving, M.; and Engelhardt, M.: Microstructure of cu damascene nano-interconnects. Proceedings of Advanced Metallization Conference (AMC) , 397 (2002)

    Google Scholar 

  7. Ogawa, E. T.; McPherson, J. W.; Rosal, J. A.; Dickerson, K. J.; Chiu, T. C.; Tsung, L. Y.; Jain, M. K.; BonifieldT. D.; Ondrusek J. C.; and McKee, W. R.: Stress-induced voiding under vias connected to wide Cu metal leads. International Reliability Physics Symposium 2002 (USA) 312 (2002)

    Google Scholar 

  8. Kawano, M.; Fukase, T.; Yamamoto, Y.; Ito, T.; Yokogawa, S.; Tsuda, H.; Kunimune, Y.; Saitoh, T.; Ueno, K.; and Sekine, M.: Stress relaxation in Dual-damascene Cu Interconnects to Suppress Stress-induced Voiding. IEEE International Interconnect Technology Conference 2003, 210 (2003)

    Google Scholar 

  9. Yoshida, K.; Fujimaki, T.; Miyamoto, K.; Honma, T.; Kaneko, H.; Nakazawa H.; and Morita, M.: Stress induced voiding phenomena for actual CMOS LSI interconnects, 2002 International Electron Devices Meeting. Technical Digest (USA) 753 (2002)

    Google Scholar 

  10. Usami, T.; Shimokawa, K.; and Yoshimaru, M.: Low dielectric constant interlayer using fluorine-doped silicon oxide. Jpn. J. Appl. Phys. 33(1B), 408(1994)

    Article  Google Scholar 

  11. Miyajima, H.; Katsumata, R.; Nakasaki, Y.; Nishiyama, Y.; and Hayasaka, N.: Water absorption properties of fluorine-doped SiO2 films using plasma-enhanced chemical vapor deposition. Jpn. J. Appl. Phys. 35(12A), 6217 (1996)

    Article  CAS  Google Scholar 

  12. Loboda, M. J.: New solutions for intermetal dielectrics using trimethylsilane-based PECVD processes. Microelectron. Eng. 50(1–4), 15 (2000)

    Article  CAS  Google Scholar 

  13. Sugiarto, D.; Lee, P.; Oka, N.; Iwasaki, N.; and Ishikawa, Y.: Integration of Carbon Doped Oxide-CVD low-k dielectric film for damascene Cu interconnection, Advanced Metallization Conference 2001 (AMC 2001). Proceedings of the Conference (USA) 337 (2001)

    Google Scholar 

  14. Inohara, M.; Tamura, I.; Yamaguchi, T.; Koike, H.; Enomoto, Y.; Arakawa, S.; Watanabe, T.; Ide, E.; Kadomura, S.; and Sunouchi, K.: High performance copper and low-k interconnect technology fully compatible to 90 nm-node SOC application (CMOS4). 2002 International Electron Devices Meeting. Technical Digest (USA) 77 (2002)

    Google Scholar 

  15. Miyajima, H.; Watanabe, K.; Fujita, K.; Ito, S.; Tabuchi, K.; Shimayama, T.; Akiyama, K.; Hachiya, T.; Higashi, K.; Nakamura, N.; Kajita, A.; Matsunaga, N.; Enomoto, Y.; Kanamura, R.; Inohara, R.; Honda, K.; Kamijo,H.; Nakata, R.; Yano, H.; Hayasaka, N.; Hasegawa, T.; Kadomura, S.; Shibata, H.; and Yoda, T.: Challenge of low-k materials for 130, 90, 65 nm node interconnect technology and beyond. 2004 International Electron Devices Meeting (USA) 329 (2005)

    Google Scholar 

  16. Abe, J.; Hayashi, H.; Kishigami, D.; Sato, Y.; Shiobara, E.; Shibata, T.; Onishi, Y.; and Ohiwa, T.: A new stacked mask process (S-MAP) utilizing spun-on carbon film for sub-130 nm etching. Proceeding of International Symposium on Dry Process (DPS2001) (Japan) , 187 (2001)

    Google Scholar 

  17. Higashi, K.; Nakamura, N.; Miyajima, H.; Satoh, S.; Kojima, A.; Abe, J.; Nagahata, K.; Tatsumi, T.; Tabuchi, K.; Hasegawa, T.; Kawashima, H.; Arakawa, S.; Matsunaga, N.; and Shibata, H.: Manufacturable copper/low-k SiOC/SiCN process technology for 90 nm-node high performance eDRAM. Proceedings of the IEEE 2002 International Interconnect Technology Conference (USA) 5 (2002)

    Google Scholar 

  18. Hu, C.-K.; Rosenberg, R.; Rathore, H. S.; Nguyen, D. B.; and Agarwala, B.: Scaling effect on electromigration in on-chip Cu wiring. Proceedings of the IEEE 1999 International Interconnect Technology Conference (USA) 267 (1999)

    Google Scholar 

  19. Hatano, M.; Usui, T.; Shimooka, Y.; and Kaneko, H.: EM lifetime improvement of Cu Damascene interconnects by p-SiC cap layer. Proceedings of the IEEE 2002 International Interconnect Technology Conference (USA) 212 (2002)

    Google Scholar 

  20. Grill, A. and Patel, V.: Ultra low-k dielectrics prepared by plasma-enhanced chemical vapor deposition. Appl. Phys. Lett. 79(6), 803 (2001)

    Article  CAS  Google Scholar 

  21. Miyajima, H.; Masuda, H.; Idaka, T.; Shimayama, T.; Kagawa, Y.; Tabuchi, K.; Yano, H.; Hasegawa, T.; Kadomura, S.; and Yoda, T.: Material design of balance between high mechanical strength and high plasma resistance for porous PE-CVD SiOC film (k=2.3), Advanced Metallization Conference 2005 (AMC 2005). Proceedings of the Conference (USA) 297 (2005)

    Google Scholar 

  22. Fujita, K.; Miyajima, H.; Nakata, R.; and Miyashita, N.: Notable Improvement in Porous Low-k film Properties using Electron-Beam Cure Method. Proceedings of the IEEE 2003 International Interconnect Technology Conference (USA) 106 (2003)

    Google Scholar 

  23. Miyajima, H.; Fujita, K.; Nakata, R.; Yoda, T.; and Hayasaka, N.: The application of simultaneous ebeam cure methods for 65 nm node Cu/low-k technology with hybrid (PAE/MSX) structure. Proceedings of the IEEE 2004 International Interconnect Technology Conference (USA) 222 (2004)

    Google Scholar 

  24. Shimada, M.; Miyajima, H.; Nakata, R.; and Yoda, T.: High-performance low-k dielectric using advanced EB-cure process. Proceeding of 2001 international conference on solid state devices and materials (Japan) , 416 (2001)

    Google Scholar 

  25. Yoda, T.; Nakasaki, Y.; Hashimoto, H.; Fujita, K.; Miyajima, H.; Shimada, M.; Nakata, R.; Kaji, N.; and Hayasaka, N.: Structural Studies of High-Performance Low-k Dielectric Materials Improved by Electron-Beam Curing. Jpn. J. Appl. Phys. 44(1A), 75 (2005)

    Article  CAS  Google Scholar 

  26. Ohnishi, T.; Nagaseki, K.; Shimada, M.; Miyajima, H.; Nakata, R.; Yamaguchi, M.; Murase, J.; and Hata, H.: Advanced EB-cure process and equipment for low-k dielectric. Proceeding of 2001 IEEE International Symposium on Semiconductor Manufacturing (USA) 325 (2001)

    Google Scholar 

  27. Yoneda, K.; Kato, M.; Kondo, S.; Kobayashi, N.; Matsuki, N.; Matsushita, K.; Ohara, N.; Fukazawa, A.; and Kimura, T.: Impacts of UV cure for reliable porous PECVD SiOC integration [IC interconnect applications]. Proceedings of the IEEE 2005 International Interconnect Technology Conference (USA) 220 (2005)

    Google Scholar 

  28. Furusawa, T.; Miura, N.; Matsumoto, M.; Goto, K.; Hashii, S.; Fujiwara, Y.; Yoshikawa, K.; Yonekura, K.; Asano, Y.; Ichiki, T.; Kawanabe, N.; Matsuzawa, T.; and Matsuura, M.: UV-hardened high-modulus CVD-ULK material for 45-nm node Cu/low-k interconnects with homogeneous dielectric structures. Proceedings of the IEEE 2005 International Interconnect Technology Conference (USA) 45 (2005)

    Google Scholar 

  29. Fujita, K.; Miyajima, H.; Nakao, S.; Sakanaka, T.; Nakata, R.; Yano, H.; and Yoda, T.: Comparison between UV and EB cure method for porous PAr/porous MSX hybrid structure. Extended Abstracts of the 2005 International Conference on Solid State Device and Materials (Japan) , 298 (2005)

    Google Scholar 

  30. Kanamura, R.; Ohoka, Y.; Fukasawa, M.; Tabuchi, K.; Nagahata, K.; Shibuki, S.; Muramatsu, M.; Miyajima, Usui, H. T.; Kajita, T.; Shibata, H.; and Kadomura, S.: Integration of Cu/low-k dual-Damascene interconnects with a porous PAE/SiOC hybrid structure for 65 nm-node high performance eDRAMS. 2003 Symposium on VLSI Technology. Digest of Technical Papers (Japan) , 107 (2003)

    Google Scholar 

  31. Kajita, A.; Usui, T.; Yamada, M.; Ogawa, E.; Katata, T.; Sakata, A.; Miyajima, H.; Kojima, A.; Kanamura, R.; Ohoka, Y.; Kawashima, H.; Tabuchi, K.; Nagahata, K.; Kato, Y.; Hayashi, T.; Kadomura, S.; and Shibata, H.: Highly reliable Cu/low-k dual-damascene interconnect technology with hybrid (PAE/SiOC) dielectrics for 65 nm-node high performance eDRAM. Proceedings of the IEEE 2003 International Interconnect Technology Conference (USA) 9 (2003)

    Google Scholar 

  32. Honda, K.; Kanda, M.; Ishizuka, R.; Moriuchi, Y.; Matsubara, Y.; Habu, M.; Yoshida, T.; Matsuda, S.; Kittaka, H.; Miyajima, H.; Hachiya, T.; Kajita, A. Usui, T.; Nagashima, N.; Kanamura, R.; Okamoto, Y.; Yamada, S.; and Noguchi, T.: Integration of interconnect process highly manufacturable for 65 nm CMOS platform technology (CMOS5). 2004 Symposium on VLSI Technology. Digest of Technical Papers (USA) 62 (2004)

    Google Scholar 

  33. Matsunaga, N.; Nakamura, N.; Higashi, K.; Yamaguchi, H; Watanabe,T.; Akiyama, K.; Nakao, S.; Fujita, K.; Miyajima, H.; Omoto, S.; Sataka, A.; Katata, T.; kagawa, Y.; Kawashima, H.; Enomoto, Y.; Hasegawa, T.; and Shibata, H.: BEOL process integration technology for 45 nm node porous low-k/Copper interconnects. Proceedings of the IEEE 2005 International Interconnect Technology Conference (USA) 6 (2005)

    Google Scholar 

  34. Fujimaki, T.; Higashi, K.; Nakamura, N.; Matsunaga, N.; Yoshida, K.; Miyawaki, N.; Hatano, M.; Hasunuma, M.; Wada, J.; Nishioka, T.; Akiyama, K.; Kawashima, H.; Enomoto, Y.; Hasegawa, T.; Honda, K.; Iwai, M.; Yamada, S.; and Matsuoka, F.: Mechanism of moisture uptake induced via failure and its impact on 45 nm node interconnect design. 2005 International Electron Devices Meeting (USA) 191 (2005)

    Google Scholar 

  35. Dauskardt, R. H.; Lane, M.; Ma, Q.; Krishna, N.: Adhesion and debonding of multi-layer thin film structures. Eng. Fract. Mech. 61(1), 141 (1998)

    Article  Google Scholar 

  36. Kitsutaka, H.; Suzuki, K.; Inoto, H.; Kawakami, M.; Honda, K.; Hasunuma, M.; Ito, S.; Miyajima, H.; Fujita, K.; Kaneko, H.; Yoda, T.; Oyamatsu, H.; Yamada, S.; Matsuoka, F.; and Noguchi, T.: Improvement of interfacial adhesion in chip-package interaction of 65 nm node SoC. Advanced Metallization Conference 2004 (AMC 2004) (USA) 265 (2005)

    Google Scholar 

  37. Nakamura, N.; Yoshizawa, T.; Watanabe, T.; Miyajima, H.; Nakao, S.; Yamada, N.; Fujita, K.; Matsunaga, N.; and Shibata, H.: A plasma damage resistant ultra low-k hybrid dielectric structure for 45 nm node copper dual-damascene interconnects. Proceedings of the IEEE 2004 International Interconnect Technology Conference (USA) 228 (2004)

    Google Scholar 

  38. Nakamura, T. and Nakashima, A.: Robust Multilevel Interconnects with a Nano-clustering Porous Low-k (k<2.3). Proceedings of the IEEE 2004 International Interconnect Technology Conference (USA) 175 (2004)

    Google Scholar 

  39. Nihei, M.; Horibe, M.; Kawabata, A.; and Awano, Y.: Carbon nanotube vias for future LSI interconnects. IEEE International Interconnect Technology Conference 2004 (USA) 251 (2004)

    Google Scholar 

  40. Ogawa, E. T.; McPherson, J. W.; Rosal, J. A.; Dickerson, K. J.; Chiu, T. C.; Tsung, L. Y.; Jain, M. K.; BonifieldT. D.; Ondrusek, J. C.; and McKee, W. R.: Stress-induced voiding under vias connected to wide Cu metal leads. 2002 International Reliability Physics Symposium(USA) 312 (2002)

    Google Scholar 

  41. Kawano, M.; Fukase, T.; Yamamoto, Y.; Ito, T.; Yokogawa, S.; Tsuda, H.; Kunimune, Y.; Saitoh, T.; Ueno, K.; and Sekine, M.: Stress relaxation in Dual-damascene Cu Interconnects to Suppress Stress-induced Voiding. IEEE International Interconnect Technology Conference 2003 (USA) 210 (2003)

    Google Scholar 

  42. Yoshida, K.; Fujimaki, T.; Miyamoto, K.; Honma, T.; Kaneko, H.; Nakazawa, H.; and Morita, M.: Stress induced voiding phenomena for actual CMOS LSI interconnects. 2002 International Electron Devices Meeting (USA) 753 (2002)

    Google Scholar 

  43. Huang, T.C.; Yao, C.H.; Wan, W.K.; Hsia, C. C.; and Liang, M.S.: Numerical modeling and characterization of the stress migration behavior upon various 90 nanometer Cu/Low-k interconnects. IEEE International Interconnect Technology Conference 2003 (USA) 207 (2003)

    Google Scholar 

  44. Okazaki, M.; Hatano, M.; Yoshida, K.; Shibasaki,S.; Kaneko, H.; Yoda T.; and Hayasaka, N.: Sea of Kelvin Multiple-pattern arrangement interconnect characterization for Low-k/Cu dual Damascene and its findings. IEEE International Interconnect Technology Conference 2004 (USA) 211 (2004)

    Google Scholar 

  45. Shimada, M.; Otsuka, Y.; Harada, T.; Tsutsumida, A.; Inukai, K.; Hashimoto, H.; and Ogawa, S.: 2-Dimentional distribution of Dielectric Constants in Patterned Low-k Structures by a nm-probe STEM/Valence EELS (V-EELS) Technique. IEEE International Interconnect Technology Conference 2005 (USA) 88 (2005)

    Google Scholar 

  46. Otsuka, Y.; Harada, T.; Ito, T.; Tsutsumida, A.; Shimada, M.; Inukai, K.; Hashimoto, H.; and Ogawa, S.: TEM-EELS 2-Dimensinal Characterization of Damage in Patterned Low-k Dielectric Films. Advanced Metallization Conference Asian Session 2004, Mat. Res. Soc. ULSI-XX(Japan) , 425 (2005)

    Google Scholar 

  47. Lo, S.-C.; Kai, J.-J.; Chen, F.-R.; Chang, L.; Chen, L.-C.; Chiang, C.-C.; Ding, P.; Chin, B.; Zhang. H.; and Chen, F.: Four-dimensional dielectric property image obtained from electron spectroscopic imaging series. J. Electron Microsc. 50(6), 497 (2001)

    Article  CAS  Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Advanced ULSI Process Engineering Department, Process & Manufacturing Engineering Center Toshiba Corporation Semiconductor Company, 8 Shinsugita-cho, Isogo-ku, 235-8522, Yokohama, Japan

    T. Yoda & H. Miyajima

Authors
  1. T. Yoda
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. H. Miyajima
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to T. Yoda .

Editor information

Editors and Affiliations

  1. Tel Aviv University, Ramat Aviv, Tel Aviv, 69978, Israel

    Yosi Shacham-Diamand

  2. Dept. Applied Chemistry, Waseda University, Okubo 3-4-1 , Tokyo, 169-8555, Japan

    Tetsuya Osaka

  3. Emerson Network Power, Cooligy Precision Cooling, Maude Avenue 800, Mountain View, 94043, U.S.A.

    Madhav Datta

  4. Division of Corporate Relations, The University of Tokyo, Hongo 7-3-1, Tokyo , 113-8654, Japan

    Takayuki Ohba

Rights and permissions

Reprints and permissions

Copyright information

© 2009 Springer Science+Business Media, LLC

About this chapter

Cite this chapter

Yoda, T., Miyajima, H. (2009). Advanced BEOL Technology Overview. In: Shacham-Diamand, Y., Osaka , T., Datta, M., Ohba, T. (eds) Advanced Nanoscale ULSI Interconnects: Fundamentals and Applications. Springer, New York, NY. https://doi.org/10.1007/978-0-387-95868-2_19

Download citation

Publish with us

Policies and ethics

Search

Navigation