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Circuit Architectures for 3D Integration

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Wafer Level 3-D ICs Process Technology

Part of the book series: Integrated Circuits and Systems ((ICIR))

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Author information

Authors and Affiliations

  1. Lincoln Laboratory, Massachusetts Institute of Technology, Lexington, MA, USA

    Nisha Checka

Authors
  1. Nisha Checka
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Correspondence to Nisha Checka .

Editor information

Editors and Affiliations

  1. School Electrical & Electronic Eng., Photonics Res. Centre, Nanyang Technological University, Singapore, 639798, Singapore

    Chuan Seng Tan

  2. Center for Integrated Electronics, Rensselaer Polytechnic Institute, 8th Street 110, Troy, 12180, U.S.A.

    Ronald J. Gutmann

  3. Dept. Electrical Engineering, Massachusetts Institute of Technology, Massachusetts Ave. 77, Cambridge, 02139, U.S.A.

    L. Rafael Reif

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Checka, N. (2008). Circuit Architectures for 3D Integration. In: Tan, C., Gutmann, R., Reif, L. (eds) Wafer Level 3-D ICs Process Technology. Integrated Circuits and Systems. Springer, Boston, MA. https://doi.org/10.1007/978-0-387-76534-1_13

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  • DOI: https://doi.org/10.1007/978-0-387-76534-1_13

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  • Publisher Name: Springer, Boston, MA

  • Print ISBN: 978-0-387-76532-7

  • Online ISBN: 978-0-387-76534-1

  • eBook Packages: EngineeringEngineering (R0)

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